Control Voltage Of Voltage-controlled Oscillator Research Articles

A 24 GHz FMCW/Doppler Dual-Mode Frequency Synthesizer With 68.8 kHz RMS FM Error and 1.25 GHz Chirp Bandwidth

This brief presents a 24 GHz dual-mode frequency synthesizer designed in a 55-nm CMOS technology supporting both Doppler and frequency modulated continuous wave (FMCW) radars. The effects of chirp linearity and delta-sigma modulation (DSM) resolution on the rms FM error is analyzed. A design procedure for the PLL loop bandwidth and time interval of the frequency step to reduce the rms FM error is proposed. A voltage-controlled oscillator (VCO) featuring a four-coil transformer load is developed providing differential local oscillation (LO) signals for the transmitter (TX) and quadrature LO signals for the 2-channel receiver (RX). The prototype is designed with a loop bandwidth of 350 kHz, a frequency step time interval of <inline-formula> <tex-math notation="LaTeX">$2 ~\mu s$ </tex-math></inline-formula>, and a VCO tuning linearity of 26&#x0025;. In the FMCW mode, it achieved an rms FM error of 68.8 kHz over a 1.25 GHz chirp bandwidth. In the Doppler mode, the VCO operates in the free-running mode to save power consumption. An 8-bit digital-to-analog converter (DAC) is used to provide the VCO control voltage compensating process and voltage variations. The free-running VCO operates at a 24.125 GHz and has a frequency error of less than 1 MHz.

A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector

This brief presents a 2-GHz dividerless injection-locked phase-locked loop (PLL) (ILPLL) with a voltage-controlled oscillator (VCO) control voltage ripple-compensated phase detector (PD) (RICPD). The proposed lock detector (LD) can detect not only the frequency difference between VCO frequency and target frequency but also the coarse phase position. With the help of the LD, the RICPD has a simple architecture using AND gates, relieving mismatches in the PD and charge pump. Additionally, the RICPD improves the performance of phase noise by a ripple compensation technique and solves an UP/DN pulse mismatch problem of PLL with a simple structure. As a result, the proposed ILPLL improves jitter performance by 21% (471-fs integrated jitter from 1 kHz to 40 MHz). The test core fabricated in a 65-nm CMOS process consumes 6.2 mW.

A 0.009–1.4-GHz Frequency Synthesizer With Suppressed Transients During VCO Band Switching

This brief presents a 0.009–1.4-GHz frequency synthesizer that is able to compensate for changes in the frequency tuning range, due to temperature variations, by switching voltage-controlled oscillator (VCO) bands with minimal phase and frequency errors, without cycle slipping and without introducing any phase offsets. This is accomplished by a subthreshold capacitor bank switching circuit that causes the gradual addition of capacitance slowly enough to allow the loop to adjust the VCO control voltage to compensate. The additional circuitry uses less than 0.001 mm2 of silicon area and has minimal power consumption and minimal effects on the synthesizer's phase noise when fully switched. The synthesizer used to demonstrate this was implemented in a 0.18- $\mu\mbox{m}$ SiGe BiCMOS process and achieves 365-fs integrated jitter at 1.05 GHz, with a total power consumption of 81 mW. Measurements of the capacitor bank switching circuit shows that it prevents cycle slipping during band switching and reduces the maximum frequency deviation by 99.3%.

Ring VCO Design with Variable Capacitance XNOR Delay Cell

This paper presents the new designs of voltage controlled oscillator (VCO) with three transistors XNOR gate as variable capacitive load. Design of three, five and seven stage VCO have been reported using single ended ring topology. CMOS inverter based delay cell is modified with addition of XNOR capacitive load. Output frequency has been controlled by applied voltage to variable capacitive load. Control voltage of VCO has been varied from 1.3 to 2.1 V. Three stage VCO provides output frequency variation in the range of 3.52–3.34 GHz with power consumption variation from 0.81 to 1.76 mW. Five stage VCO shows frequency variation from 2.06 to 1.98 GHz with power consumption varying from 1.35 to 2.94 mW. Moreover, frequency of seven stage VCO varies from 1.47 to 1.41 GHz with varying power from 1.89 to 4.12 mW. Power consumption and output frequency of proposed VCO circuits have been compared with earlier reported circuits and present approach shows considerable improvements.

Multi‐band VCO PLL with continuously maintained optimum VCO control voltage

A new architecture for a multi-band voltage-controlled oscillator (VCO) phase-locked loop (PLL) is presented, which can continuously maintain the optimum VCO sub-band and the VCO control voltage even with severe supply voltage variation. A prototype 2 GHz PLL with the new architecture is successfully demonstrated in 0.13 µm CMOS technology.

An Ultra-Low-Power Super Regeneration Oscillator-Based Transceiver With 177-$\mu$W Leakage-Compensated PLL and Automatic Quench Waveform Generator

An ultra-low-power super regeneration oscillator (SRO) transceiver with a 177- μW ultra-low-power phase-locked loop (PLL) and automatic quench waveform generator (QWG) is presented. In order to decrease the PLL power consumption, the leakage current is measured at the VCO control voltage node, and the control voltage is compensated by the digital part. As a result, the frequency can be maintained near 2.37 GHz after the PLL is turned off. An automatic QWG circuit that can search for the critical current of the SRO automatically is proposed in order to mitigate the process, voltage, temperature variations of the conventional QWG. This chip is implemented using 90-nm CMOS technology. The die area of the full transceiver is 3 mm × 4 mm and that of the PLL is 0.4 mm × 0.9 mm. The leakage compensation and high-Q voltage-controlled oscillator (VCO) approach results in a frequency offset of 70 kHz and fluctuation of ±75 kHz (the maximum frequency error is 145 kHz at 60 ppm). The phase noise of the VCO output at 2.37 GHz is -103.5 dBc/Hz at 1-MHz offset. The average power consumption of the PLL is 177 μW from a 1.2-V supply voltage.

Phase-locked noncontact scanning force microscope

A new tip height control system for noncontact scanning force microscope (SFM) utilizing the phase-lock technology is proposed. Its most extensive feature is that the system is unconditionally stable whereas the conventional control systems have difficulties in stability especially when the tip is at close proximity to the sample surface. In this new system, an oscillator using the cantilever as a mechanical resonator is used as a voltage controlled oscillator (VCO) in a phase-locked loop. Its output signal phase is locked to a high precision frequency source. The force gradient detected by the cantilever equivalently alters the VCO control voltage, which is detected as a compensational signal of the loop filter output. The phase-lock technique made it possible to reduce the tip height to an extent which was impossible with the conventional servo technology. Thus this new control technique is expected to be effective in improving the resolution of the noncontact SFM.

Frequency stabilization of an LM566 VCO used in wide-band FM generation

The frequency stability problem, especially due to power supply variation, has been studied for an LM566 voltage controlled oscillator (VCO) used in the direct generation of wide-band FM. A simple scheme, based on premodulating the modulation component of the VCO control voltage, in accordance with the power supply variation, has been suggested for achieving frequency stability of the FM generator. The proposed stabilization circuit has been implemented and tested for satisfactory operation.