Continuous-time Architecture Research Articles

A Fully Integrated Current-Mode Continuous-Time Delta-Sigma Modulator for Biological Nanopore Read Out.

This paper presents a fully integrated low noise current-to-digital converter based on current-mode continuous-time delta-sigma modulators (CT DSMs). The circuit was realized in standard 0.35 μm complimentary metal-oxide-semiconductor process and achieves a noise floor as low as 200fA rms within a bandwidth of 10kHz. Thanks to the continuous-time architecture, the oversampling together with the implicit anti-aliasing behavior of the current-mode CT DSM prevents the back folding of any out-of-band signals and noises. Running at a sampling frequency of 1.6MHz, the circuit achieves a measured worst case anti-aliasing filtering of -110dB for an out-of-band signal at 1.59MHz. This characteristic eliminates the need of an anti-aliasing filter, which reduces the complexity as well as the area and power consumption. Two feedback versions, a transistor based as well as a capacitor-based current division have been used to reduce the reference current noise. The transistor-based current division feedback modulator consumes a power of 6.73mW and occupies an area of 0.63mm 2, whereas the capacitor based consumes a power of 4.6mW and occupies an area of 0.32mm 2. Both of them operate at a supply voltage of ±1.5V.

A Fully Integrated Silicon-Carbide Sigma–Delta Modulator Operating up to 500 °C

This paper presents the first fully integrated sigma-delta modulator implemented in an in-house silicon carbide (SiC) bipolar technology for high-temperature applications. A second-order 1-b continuous-time architecture is adopted. Dual-loop compensation technique is employed to accommodate one clock period comparator delay. The circuits are designed to have enough margins without degrading the modulator's performance, considering the variation of device parameters over a large temperature range. The measurement results show that from room temperature to 500°C, the modulator's peak SNDR is constant around 30 dB at a clock speed of 512 kHz. The chip area of the modulator is 6.9 mm × 2.8 mm with one metal layer. It consumes around 1 W from a 15 V power supply. This paper demonstrates the feasibility to further develop highly integrated SiC bipolar junction transistor integrated circuits for extremely high-temperature sensing applications.

Linearity analysis of closed-loop capacitive accelerometer due to distance mismatch between plates and the influence of compensation capacitor array

This paper presents mathematical formulae showing that the distance mismatch for an uncentered proof mass in an accelerator sensor does not influence the linearity of the closed-loop accelerometer as a whole. This asymmetry in sensors only introduces an output voltage offset in the readout integrated circuit. Numerical simulation using Matlab/Simulink confirms the mathematical conclusion. The linear response after compensation with a conventional capacitor array is also simulated and analyzed. Results show that there is a loss in linearity. Similar results hold not only for the continuous-time architecture, but also for a time-divided architecture. A readout integrated circuit with a time-divided architecture is designed and fabricated using a 0.35 μm HV CMOS process. An accelerometer composed of a microelectromechanical system sensor with severe built-in distance mismatch and the designed readout integrated circuit is tested. Test results show that the nonlinearity of such accelerometer is within 0.3%.

MEMS gyroscope control system using a band-pass continuous-time sigma-delta modulator

This paper presents a MEMS gyroscope control system of using a high-order band-pass continuous-time sigma-delta modulator. Compared with a low-pass discrete-time sigma-delta modulator based solution, the band-pass modulator can considerably decrease the sampling frequency; moreover, the continuous-time architecture has an obvious advantage on PCB prototyping and shorter lead time of the implementation in hardware. System level simulations using MATLAB/Simulink show the proposed sixth order sigma-delta modulator can achieve a high SNR of 100 dB for an angular rate input with an amplitude of 200°/s and a frequency of 32 Hz. A PCB circuit implementation is simulated using Orcad/PSpice to analyze the stability, and implemented in hardware. Measurement of the power spectral density of the output bitstream reveals a noise floor of −90 dBV/Hz1/2. The prototype is tested on a rate table with an angular rate input, verifying that the principle of the approach of using an electro-mechanical band-pass sigma-delta modulator control system for a MEMS gyroscope.

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.