Continuous-time Analog Filters Research Articles

Continuous-Time Analog Filters for Audio Edge Intelligence: Review on Circuit Designs [Feature

Edge audio devices can reduce data bandwidth requirements by pre-processing input speech on the device before transmission to the cloud. As edge devices are required to ensure always-on operation, their stringent power constraints pose several design challenges and force IC designers to look for solutions that use low standby power. One promising bio-inspired approach is to combine the continuous-time analog filter channels with a small memory footprint deep neural network that is trained on edge tasks such as keyword spotting, thereby allowing all blocks to be embedded in an IC. This paper reviews the historical background of the continuous-time analog filter circuits that have been used as feature extractors for current edge audio devices. Starting from the interpretation of a basic biquad filter as a two-integrator-loop topology, we introduce the progression in the design of second-order low-pass and band-pass filters ranging from OTA-based to source-follower-based architectures. We also derive and analyze the small-signal transfer function and discuss their usage in edge audio applications.

64 dB Dynamic-Range 810 μW 90 MHz Fully-Differential Flipped-Source-Follower Analog Filter in 28nm-CMOS

This brief presents a 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -order continuous-time analog filter based on Flipped-Source-Follower stage. Source-Follower (SF) filters typically adopt pseudo-differential topology (critical for matching and bulk/substrate noise rejection) and are realized in not recent CMOS processes (130nm or 180nm) due to the intrinsic voltage headroom required by SF operation. The proposed device solves the above limitations by proposing a fully-differential circuital topology, which improves by 13 dB the power supply rejection with respect to pseudo differential approach, and by operating in 28nm-CMOS process, thanks to a proper level-shifter transistor, which enables optimum biasing point and enhances filter dynamic range. The prototype is composed by the cascade of two biquadratic cells. It features 90 MHz -3 dB bandwidth, and consumes 816 μW power (408 μW per cell) from a 1V supply. Dynamic-Range is 64 dB with 140 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> RMS</sub> output noise, and at 0.32 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0-PEAK</sub> differential output voltage swing. Figure-of-Merit is 156 dBJ $^{-1}$ .

A 28 nm CMOS 100 MHz 67 dB-Dynamic-Range 968 µW Flipped-Source-Follower Analog Filter

This paper presents a fourth-order continuous-time analog filter based on the cascade of two flipped-source-follower (FSF) biquadratic (biquad) cells. The FSF biquad adopts two interacting loops (the first due to the classic source-follower, and the second to the additional gain path) which lower the impedances of all circuit nodes with relevant benefits in terms of noise power reduction and linearity enhancement. The presented device was integrated in 28 nm CMOS and featured 100 MHz −3 dB bandwidth with 67 dB Dynamic-Range. Input IP3 was 12 dBm at 10 and 11 MHz input tone frequencies. Total power consumption was 0.968 mW (0.484 mW per cell). Hence, the filter performed one of the highest figures-of-merit (160.7 dBJ-1) compared with analog state-of-the-art filters.

Time-Domain Operational Amplifier With Voltage-Controlled Oscillator and Its Application to Active-RC Analog Filter

Time-domain operational amplifier (op-amp) is developed with only time-domain circuits such as voltage-controlled oscillator (VCO) and voltage-controlled delay line (VCDL). The infinite dc-gain of the voltage-to-phase transfer characteristic of VCO allows the time-domain op-amp to have large dc-gain. The frequency compensation is performed by the left-half plane (LHP) zero created by VCDL whose output phase is proportional to its control input voltage. With the proposed time-domain op-amp, a fourth-order continuous-time (CT) analog filter with 25 MHz cut-off frequency has been implemented in a 65 nm CMOS technology. The filter occupies 0.107 mm2and operates with 0.9 V supply consuming 8.2 mW. The measured in-band input third-order intercept point (IIP3) is 22.6 dBm and the peak signal-to-noise+distortion ratio (SNDR) is 60.9 dB.

CMOS analog filter design using the Proportional Source Transconductances Integrator

This work assesses the applicability of a compact CMOS current-mode companding integrator in the design of analog continuous-time filters with high linearity. The companding integrator is based on the proportionality between the source transconductances of the input and output MOS transistors and is independent of the inversion level of the devices. The circuit has been designed in CMOS 130 nm technology with approximately 90 μm2 total active area including biasing elements. According to simulation results the integrator performs a useful frequency bandwidth of up to 4 MHz and a third order intermodulation distortion smaller than −47 dB for input amplitudes ranging from 100 nA to 1 μA. The small and large signal responses and the third order intermodulation, among other features, have also been analyzed through simulation for a fourth order low-pass filter and a sixth order bandpass filter. Performance is compared with a CMOS log-domain integrator and filter.

Continuous-time analog filter with passband constant IIP3 based on common-gate amplifier

This paper presents an analog filter based on Rauch biquadratic cell. The filter exploits an improved analog stage that makes linearity performance uniform over the entire pass-band frequency region. All feedback analog filters suffer from poor linearity when the input tones frequency is in close proximity to the closed-loop poles frequency, where loop-gain reduces. This often forces an overdesign with higher current (higher power consumption) and/or higher overdrive voltages (lower dynamic range) in order to meet the linearity specifications over the whole filter pass-band region. The hereby proposed Rauch scheme resolves such a binding issue without power increasing and having the same IIP3 at low and at high frequency (up to the filter closed-loop poles frequency). Hence the linearity performance is in first approximation independent on the input tones bandwidth. In order to validate the hereby proposed idea a 4th-order 25 MHz −3 dB bandwidth pseudo-differential filter has been designed and simulated in CMOS 28 nm technology. The prototype consumes 820 µW from 1 V supply voltage and has 15 and 13 dBm IIP3 at 5 and 6 and 20 and 21 MHz input tones, respectively.

A 33 MHz 70 dB-SNR Super-Source-Follower-Based Low-Pass Analog Filter

In this paper, a 4th-order low-pass continuous-time analog filter is presented, that is implemented with the cascade of two efficient and compact biquadratic cells, realized using the Super-Source-Follower topology. The biquadratic cell uses only two capacitors and four transistors: two transistors for the signal processing and two transistors as current sources for biasing purpose. The 4th-order filter prototype has been integrated in 0.18 µm CMOS technology. For a 33 MHz cut-off frequency, the filter performs 18 dBm-IIP3 for two tones at 2 MHz and 3 MHz, with total current of 770 µA from a single 1.8 V supply voltage.

Continuous-time analog filter in CMOS nanoscale era

Analog filters are key blocks in analog signal processing. They are widely employed in many systems, like wireless transceivers, detectors read-out, sensors interfaces, etc. The IC technology choice for such systems is mainly dictated by the requirements of high speed and low power consumption of digital circuits. This pushed an impressive movement towards scaled technology and this has important consequences on the analog circuits design. The impact of technology scaling down to nanometre scale on analog filters design is here investigated. For instance, supply voltage reduction in analog filters limits circuits design solutions and could result in higher power consumption. Moreover, at the same time, innovative systems push analog filters to get higher and higher operation frequencies, due to the increasing bandwidth/speed requirements. Recent solutions for efficient low-voltage and high frequency analog filters in nanometre technology are described.

Oscillation-based analog diagnosis using artificial neural networks based inference mechanism

In this paper, Oscillation-Based Diagnosis (OBD) of analog electronic circuits, derived from Oscillation-Based Test (OBT), is described for the first time. OBT is an effective and simple solution to the testing problem of continuous time analog filters. The inadequacy of using an infinite-gain model of the op-amps is demonstrated and a practical implementation of the theoretical concept of OBT is discussed. A realistic model of the op-amp is therefore implemented. A fault dictionary is created and used to perform diagnosis, with artificial neural networks (ANNs) as classifiers. The robustness of the ANN diagnostic concept is demonstrated by the addition of white noise to the “measured” signals. The effectiveness of OBD is demonstrated by testing and diagnosis of a second order notch cell, realized with one operational amplifier. Single soft and catastrophic faults are considered in detail and an example of the diagnosis of double soft faults is also presented.

DVCC-based Electronically Tunable First-Order Current-mode Filters

The advent of differential voltage current conveyor (DVCC) has opened up new avenues in analog circuit design. In the present work, a DVCC has been employed to design currentmode first-order continuous-time analog filters. Parameter tunability is achieved by the use of a two-MOSFET electronic resistor which exhibits variation in resistance in accordance with a control voltage. The proposed circuits are amenable for monolithic integration by virtue of the fact that only MOSFETs and grounded capacitors are utilized. Circuit simulations using PSPICE yielded promising results.

Dynamic modeling of tunable analog integrated filters for a stability study of on-chip automatic tuning loops

Continuous-time filters with automatic tuning loops are nonlinear feedback systems that are potentially unstable. To ensure stability, particularly if the design of the loop controllers is to be improved, the appropriate linear dynamic modeling of the tunable filter, including control inputs, should be attained. This work aims to present a general dynamic modeling of continuous-time analog filters with automatic tuning capability. The general analysis leads to an equivalent small-signal linearized incremental model, from which transfer functions between output variables and control voltages are obtained. Subsequent to the analysis, it is possible to design compensated loops with enhanced stability and dynamic performance. By way of example, the modeling of a particular band-pass CMOS continuous-time analog filter is presented in this paper. Two transfer functions are derived: the transfer function between the output phase shift and the central frequency control voltage, and that between the output amplitude and the quality factor control voltage. These functions are required to properly tune the central frequency and quality factor parameters. This modeling makes it possible to propose an adaptive controller with improved stability and a possible implementation for such a controller. Finally, experimental results are shown for a CMOS 0.8 μm technology.

A Field-Programmable Analog Array of 55 Digitally Tunable OTAs in a Hexagonal Lattice

This paper reports on a field-programmable analog array (FPAA) for high-frequency continuous-time analog filters. A rapid-prototyping hardware is presented, which implements a unique hexagonal lattice topology of 55 tunable Gm cells for reconfigurable instantiation of Gm-C filters in a 0.13 mum CMOS technology. The typical power dissipation is 70 mW at a 1.2 V supply. The chip structure allows intuitive mapping of Gm-C filter schematics with up to seven independent nodes, immediate download to the hardware, and evaluation on the working prototype. Implementations of first- and second-order low-pass and sixth-order bandpass filters are presented and show the feasibility of the array for frequencies up to the order of one hundred MHz.

A G m -C continuous-time analog filter for IEEE 802.11 a/b/g/n wireless LANs

A CMOS transconductor for multi-mode wireless channel selection filter is presented. The linear transconductor is designed based on the flipped-voltage follower (FVF) circuit and an active resistor to achieve the transconductance tuning. The transconductance tuning can be obtained by changing the bias current of the active resistor. A third-order Butterworth low-pass filter implemented with the transconductors was designed by TSMC 0.18-μm CMOS process. The results show that the filter can operate with the cutoff frequency of 10---20 MHz. The tuning range would be suitable for the specifications of IEEE 802.11 a/b/g/n Wireless LANs under the consideration of saving chip areas. In the design, the maximum power consumption is 13 mW with the cutoff frequency of 20 MHz under a 1.8 V supply voltage.

Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling

This paper presents a novel algorithm for synthesis of continuous-time analog filters. The goal is to find as many "very good" design points as possible without requiring feasible designs as starting points or any other additional designer knowledge as input. This problem is challenging for present exploration-based analog-synthesis methods, including existing commercial tools, which have difficulties in locating diverse constraint-satisfying designs. The proposed algorithm conducts a three-step refinement process, in which poor-quality solution-space regions are eliminated through different strategies. It starts with the step of parameter-domain pruning, which identifies parameter subdomains that are more likely to produce many feasible solution points. Domains are found using interval arithmetic and the proposed simplified affine transformation operators. In the second step, selected variable subdomains are searched using plateau search, a novel exploration technique described in this paper. The algorithm addresses the three main types of solution-space regions: 1) convex, quasi-convex, and /spl delta/-convex regions; 2) rifts; and 3) plateau. The technique expands descendant-gradient-based search with a systematic way of sampling plateau. Finally, promising regions that remained after step 2 are further refined during the step of search with adaptive-sampling step length. Using four filter examples, experiments observed the quality of results and convergence of synthesis. Plateau search was also experimented for synthesis of two /spl Delta//spl Sigma/ modulators.

A 1 GHz CMOS analog front-end for a generalized PRML read channel

A 1 GHz CMOS analog front-end for general partial response maximum likelihood (GPRML) read channel in hard disk drive application has been implemented in 0.35 /spl mu/m CMOS. A continuous time analog filter fulfills the relaxed equalization for GPRML detection and can save up to 35% power consumption for the whole read channel. An analog DFE-based timing recovery loop is implemented to avoid the extremely long latency in the digital signal processing path (Viterbi decoder). The measured performances is 1.1 dB off simulations at 800 MHz and 1.6 dB off at 1GHz. The chip draws 240 mW from a 3.3 V supply at 800MHz clock and 380 mW from a 3.6 V supply at 1 GHz clock.

A 1.25-V Micropower&amp;gt;tex&amp;lt;$G_m$&amp;gt;/tex&amp;lt;-&amp;gt;tex&amp;lt;$C$&amp;gt;/tex&amp;lt;Filter Based on FGMOS Transistors Operating in Weak Inversion

This paper presents a novel linearized transconductor architecture working at 1.25 V in a 0.8-/spl mu/m CMOS technology with very low power consumption. The special features of the floating-gate MOS (FGMOS) transistor are combined in weak and strong inversion leading to a simplified topology with fewer stacked transistors and a very low noise floor. The design methodology is thoroughly explained, together with the advantages and disadvantages of working with the FGMOS transistor. Furthermore, second-order effects arising from nonideal behavior of the device are analyzed and limits for the performance are established. Experimental results from a second-order low-pass/bandpass filter that was implemented using the transconductor show a tunability of over one and a half decades in the audio range, a dynamic range of over 62 dB, and a maximum power consumption of 2.5 /spl mu/W. These results demonstrate the suitability of the FGMOS transistor for implementing analog continuous-time filters, while at the same time pushing down the voltage limits of process technologies and simplifying the circuit topologies to obtain significant power savings.

Design of hybrid filter banks for analog/digital conversion

This paper presents design algorithms for hybrid filter banks (HFBs) for high-speed, high-resolution conversion between analog and digital signals. The HFB is an unconventional class of filter bank that employs both analog and digital filters. When used in conjunction with an array of slower speed converters, the HFB improves the speed and resolution of the conversion compared with the standard time-interleaved array conversion technique. The analog and digital filters in the HFB must be designed so that they adequately isolate the channels and do not introduce reconstruction errors that limit the resolution of the system. To design continuous-time analog filters for HFBs, a discrete-time-to-continuous-time ("Z-to-S") transform is developed to convert a perfect reconstruction (PR) discrete-time filter bank into a near-PR HFB; a computationally efficient algorithm based on the fast Fourier transform (FFT) is developed to design the digital filters for HFBs. A two-channel HFB is designed with sixth-order continuous-time analog filters and length 64 FIR digital filters that yield -86 dB average aliasing error. To design discrete-time analog filters (e.g., switched-capacitors or charge-coupled devices) for HFBs, a lossless factorization of a PR discrete-time filter bank is used so that the reconstruction error is not affected by filter coefficient quantization. A gain normalization technique is developed to maximize the dynamic range in the finite-precision implementation. A four-channel HFB is designed with 9-bit (integer) filter coefficients. With internal precision limited to the equivalent of 15 bits, the maximum aliasing error is -70 dB, and with the equivalent of 20 bits internal precision, maximum aliasing is -100 dB. The 9-bit filter coefficients degrade the stopband attenuation (compared with unquantized coefficients) by less than 3 dB.

A class of predictive analog filters for sensor signal processing and control instrumentation

A class of analog continuous-time filters is introduced, having predictive properties for specified narrow-band signal models, such as low-order polynomials or sinusoids. Such filters are designed by using model transfer functions designed in the discrete-time domain. Z-to-s-domain mapping is done using the inverse bilinear transformation. The analog filters are implemented with active-RC structures, using the state-variable structure for biquads and a single-op-amp structure for real poles and zeros. The application examples include a filter for zero-crossing detectors, polynomial predictors for sensor signal smoothing, and an optimized sixth-order ramp-tracking filter for anti-aliasing and anti-imaging in digital signal processor (DSP) systems where high selectivity is required.

Synergy at work between continuous-time and sampled-data analog filters for integrated high-frequency, high-Q signal processing

High-frequency, high-Q-factor analog signal processing systems based on sampled-data switched-capacitor circuitry and continuous-time filters are proposed in a way that tends to combine the most advantageous aspects of both techniques. The new systems are applicable to video, radio and radar filtering functions and have unparalleled potential for producing more accurate, economical, and repeatable results than have been achieved with other methods.

Optimal dynamic range integrators

The design of optimal dynamic range integrators that are meant as building blocks for optimal dynamic range analog continuous-time filters is discussed. A fundamental limit for the dynamic range of an integrator is given. This limit is a function of the supply voltage and the available amount of capacitance. It is shown how integrators are to be designed if this limit is to be reached. Different conventional integrator realizations are evaluated and optimized so that they can be compared to the fundamental limit. A design example of a filter with integrators that approach this limit is given. >