Continuous-time Adaptive Equalizer Research Articles

Single-Chip Receiver for 1.25 Gb/s Over 50-m SI-POF

This letter presents a single chip receiver for short-reach high-speed applications through low-cost plastic optical fiber. It compensates the limited bandwidth caused by the fiber and the external photodiode. The prototype contains a transimpedance amplifier, a continuous-time adaptive equalizer, a limiting amplifier, and a clock and data recovery circuit. Experimentally, we have obtained 1.25 Gb/s transmission for a simple nonreturn to zero modulation in an optical link composed of 50 m of step-index polymer optical fiber and a large area Si p-i-n photodetector. It achieves a power under 110 mW at only 1 V of supply voltage.

Power comparator for continuous-time adaptive equalization in Ethernet-based instrumentation

Recently, Ethernet has been chosen as a replacement for standard-based instrumentation. Its performance is increasing, thanks to speeds of 1 Gbps, 10 Gbps and beyond on backplanes, which expands the instrumentation and measurement potential. However, these high-speed serial links need to be able to retain the integrity of the data stream through some type of equalization. This paper proposes a new differential power comparator, to be used in continuous-time adaptive equalizers inside these Ethernet-based instruments.

Reliable CMOS adaptive equalizer for short-haul optical networks

A new low-voltage CMOS continuous-time adaptive equalizer for short-haul gigabit optical communications is presented in this paper. It was designed to compensate the attenuation of a 1.25Gb/s signal with a simple NRZ modulation, transmitted through a 50-m length 1-mm core step-index plastic optical fiber (SI-POF). A new version of the spectrum-balancing technique is used as an adaptive criterion, achieving a simple and reliable equalization. The proposed system was designed in a cost-effective 0.18-μm CMOS process. Post-layout simulations demonstrate a signal bandwidth enhancement from 100MHz to 1.23GHz for this optical channel, with a total power consumption of 14.3mW.

Gigabit Receiver Over 1 mm SI-POF For Home Area Networks

A novel receiver front-end is proposed for short-range optical communications over low-cost polymer optical fiber and, in particular, for home area networks. This paper focuses on the experimental verification of the IC prototype POFchip-II, implemented in a standard 0.18- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex> </formula> m CMOS technology plus a commercial Si-PIN photodetector and a 1 mm step-index plastic optical fiber (POF) transmission channel. A 1.25 Gb/s data transmission rate is attained for POF lengths ranging from 10 to 50 m thanks to a continuous-time adaptive equalizer included in the receiver chain that compensates the limited and length-dependent speed of POF. The measured sensitivity of the receiver leads to an eye-safety approach up to almost 30 m reach.

A low power CMOS 3.3 Gbps continuous-time adaptive equalizer for serial link

This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of a receiver for a high-speed serial interface, which is compliant with many serial communication specifications such as USB2.0, PCI-E2.0 and Rapid IO. The low and high frequency loops are merged to decrease the effect of delay between the two paths, in addition, the infinite input impedance facilitates the cascade stages in order to improve the high frequency boosting gain. The implemented circuit architecture could facilitate the wide frequency range from 1 to 3.3 Gbps with different length FR4-PCB traces, which brings as much as 25 dB loss. The replica control circuits are injected to provide a convenient way to regulate common-mode voltage for full differential operation. In addition, AC coupling is adopted to suppress the common input from the forward stage. A prototype chip was fabricated in 0.18-μm 1P6M mixed-signal CMOS technology. The actual area is 0.6 × 0.57 mm2 and the analog equalizer operates up to 3.3 Gbps over FR4-PCB trace with 25 dB loss. The overall power dissipation is approximately 23.4 mW.

LOW-POWER, PARALLEL INTERFACE WITH CONTINUOUS-TIME ADAPTIVE PASSIVE EQUALIZER AND CROSSTALK CANCELLATION

This paper presents the low-power circuit techniques suitable for high-speed digital parallel interfaces each operating at over 10 Gbps. One potential application for such high-performance I/Os is the interface between the channel IC and the magnetic read head in future compact hard disk systems. First, a crosstalk cancellation technique using a novel data encoding scheme is introduced to suppress electromagnetic interference (EMI) generated by the adjacent parallel I/Os . This technique is implemented utilizing a novel 8-4-PAM signaling with a data look-ahead algorithm. The key circuit components in the high-speed interface transceiver including the receive sampler, the phase interpolator, and the transmitter output driver are described in detail. Designed in a 0.13-μm digital CMOS process, the transceiver consumes 310 mW per 10-Gps channel from a I-V supply based on simulation results. Next, a 20-Gbps continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components is described. Passive equalizers offer the advantages of higher bandwidth and lower power consumption compared with conventional designs using active filter. A low-power, continuous-time servo loop is designed to automatically adjust the equalizer frequency response for the optimal gain compensation. The equalizer not only adapts to different channel characteristics, but also accommodates temperature and process variations. Implemented in a 0.25-μm, 1P6M BiCMOS process, the equalizer can compensate up to 20 dB of loss at 10 GHz while only consumes 32 mW from a 2.5-V supply.

Analog complex graphic equalizer for EPR4 channels

A continuous-time analog adaptive equalizer for use in EPR4 channels in magnetic recording is presented. The equalizer is implemented as the summation of several bandpass filters covering different frequency bands as in a graphic equalizer. The outputs from each filter are weighted by a complex coefficient and summed, which results in a linear combiner structure guaranteed to minimize MSE under LMS adaptation. System-level simulations of our 'Complex Graphic Equalizer (CGE)' shows that its performance is comparable to that of a 10-tap FIR equalizer on an EPR4 channel.

A Double Loop Continuous-Time Adaptive Equalizer

This paper presents an adaptive equalizer for shorthaul gigabit optical communications. It includes two adaptation loops to compensate the changes in level and spectrum of the input signal. It consumes 29.3 mW for a 1.25 Gb/s signal, transmitted through a 50-m length 1-mm core SI-POF.