Constant Matrix Multiplication Research Articles

Construction of higher-level MDS matrices in nested SPNs

This paper presents a new construction of large-scale maximum distance separable (MDS) matrices which can be used in the design of block ciphers. We extend Cauchy matrices defined over a finite field and consider these matrices on a finite commutative ring. The resulting generalized Cauchy (GC) matrices retain the advantage of a maximum branch number. We investigate the properties of such matrices in this study. First, we provide a construction of GC matrices. The proposed construction guarantees that most of the (binary) entries in a GC matrix are zero, thereby reducing the search space for cheap GC matrices considerably. Second, we minimize the number of different sub-matrices in a GC matrix to make it more suitable for lookup table implementation, we call this a compact GC matrix. We then elaborate the structure of such compact GC matrices to consider all possible matrices and thus obtain the number of compact GC matrices. Finally, we consider the involutory potential of compact GC matrices. In particular, we prove that any compact GC matrix can be modified into an involutory one through a series of column-exchanging operations and a constant matrix multiplication. Through our experiment, we discover large-scale GC matrices, which can facilitate the future design of involutory component-based ciphers. Our best constructions can reduce the number of XOR gates in the higher-level diffusion layers in Hierocrypt-L1 and Hierocrypt-3 by 35.1% and 50%, respectively, while providing the same number of active S-boxes. Moreover, compared with the existing ones, the involutory nature of the new matrices allows for equally efficient diffusion in both encryption and decryption.

Using Transposition to Efficiently Solve Constant Matrix-Vector Multiplication and Sum of Product Problems

In this work, we present an approach to alleviate the potential benefit of adder graph algorithms by solving the transposed form of the problem and then transposing the solution. The key contribution is a systematic way to obtain the transposed realization with a minimum number of cascaded adders subject to the input realization. In this way, wide and low constant matrix multiplication problems, with sum of products as a special case, which are normally exceptionally time consuming to solve using adder graph algorithms, can be solved by first transposing the matrix and then transposing the solution. Examples show that while the relation between the adder depth of the solution to the transposed problem and the original problem is not straightforward, there are many cases where the reduction in adder cost will more than compensate for the potential increase in adder depth and result in implementations with reduced power consumption compared to using sub-expression sharing algorithms, which can both solve the original problem directly in reasonable time and guarantee a minimum adder depth.

Optimization of Constant Matrix Multiplication with Low Power and High Throughput

Constant matrix multiplication (CMM), i.e., the multiplication of a constant matrix with a vector, is a common operation in digital signal processing. It is a generalization of multiple constant multiplication (MCM) where a single variable is multiplied by a constant vector. Like MCM, CMM can be reduced to additions/subtractions and bit shifts. Finding a circuit with minimal number of add/subtract operations is known as the CMM problem. While this leads to a reduction in circuit area it may be less efficient for power consumption or throughput. It is well studied for the MCM problem that a) reducing the adder depth (AD) leads to a reduced power consumption and b) pipeline resources have to be considered during optimization to enhance throughput without wasting area. This paper addresses the optimization of CMM circuits which considers both adder depth and pipelining for the first time. For that, a heuristic is proposed which evaluates the most attractive graph topologies. It is shown that the proposed method requires 12.5% less adders with min. AD and 38.5% less pipelined operations. Synthesis results for recent FPGAs show that these reductions also translate to superior results in terms of delay and power consumption compared to the state-of-the-art.

Some Optimizations of Hardware Multiplication by Constant Matrices

This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication, i.e., multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common subexpression factorization algorithms, was implemented in a VHDL generator. Our algorithms and generator have been extended to the case of some digital filters based on multiplication by a constant matrix and delay operations. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40 percent area and speed savings are achieved.

Variable radix-2 multibit coding for 400 Mpixel/s DCT/IDCT of HDTV video decoder

Variable radix-2 multibit coding algorithm is presented and implemented in discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT). Variable radix-2 multibit coding means the 2 k signed digit (SD) representation of overlapped multibit scanning with variable shift method. SD represented by 2 k generates partial products, which can be easily implemented with shifters and adders. This algorithm is most powerful for the hardware implementation of DCT/IDCT with constant coefficient matrix multiplication. The VLSI architecture employing this algorithm shows superior performance for the parallel processing compared with the ROM-based distributed arithmetic architecture and ROM-based parallel multiplication. Since DCT/IDCT core needs matrix transposition, we propose an orthogonal transpose memory scheme that satisfies horizontal and vertical signal transfer. The simulation shows that the core is compatible with IEEE STD 1180-1990 and it runs at a rate of 400 Mpixels/s, which is up to 20 times as fast as design. The fabricated IDCT core runs at 54 MHz, features 28 latencies, consumes 0.9 W of power at 3.3 V and occupies 24 mm 2 in 0.6 μm triple metal CMOS technology for HDTV video decoder.

COMPUTATION OF TRANSFER FUNCTION MATRICES OF GENERALIZED STATE-SPACE SYSTEMS

ABSTRACT The discussion of the resolvent matrix (sI-A)−1 is extended to the generalized resolvent matrix (sE-A)−1 where E may be singular. The proof of the generalized Leverrier's relation for (sE-A)−1 is simplified by a closed-form expression of d/ds [det(sE-A)]. For the case of A being singular, the generalized Leverrier's relation can be easily transformed to the generalized Leverrier's algorithm. For the case of both E and A being singular, a new algorithm for (sE—A)−1 is developed. First, the given regular pencil (sE-A) is converted to a standard pencil by a constant matrix multiplication. Then a change of variable procedure makes the computations convenient. The two matrices problems become one matrix problems after the change of variable step. Hence, the Leverrier's algorithm can be applied. Finally, the rearrangements of scalar and matrix coefficients according to explicit formulae are needed to obtain the desired solution. After (sE-A)−1 has been computed, the transfer function matrix can be easily obtained. Two numerical examples are used to illustrate our works. This work can be applied to the discrete-time singular system also. The only difference is that the variable is z instead of s.