Constant Gate Bias Stress Research Articles

Gate Breakdown Analysis of Schottky p-GaN gate HEMTs under High Positive Gate Bias

This study investigates the gate degradation mechanisms of Schottky p-GaN gate HEMTs systemically. The constant gate bias stress is applied to investigate the gate breakdown. Schottky p-GaN Gate HEMTs show a shorter gate lifetime as gate bias increases. The gate leakage current after gate breakdown shows a resistance-like characteristic. The equivalent circuit has been proposed to discuss the gate breakdown mechanisms. When applying a high gate bias for a long time, the high electric field will damage the p-GaN gate and passivation interface and generate the percolation path. The primary gate breakdown happens between the gate and source and results in a resistance-like I–V characteristic.

Vapor-phase deposition of the fluorinated copolymer gate insulator for the p-type organic thin-film transistor

ABSTRACTA copolymer-based gate insulator was synthesized from 1,3,5-trivinyl-1,3,5-trimethyl cyclotrisiloxane (V3D3) and 3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,10-heptadecafluorodecyl methacrylate (PFDMA) via initiated chemical vapor deposition. The synthesis of the random copolymer of poly(V3D3-co-PFDMA) was confirmed by Fourier transform infrared, X-ray photoelectron spectroscopy, and water contact angle analysis. No phase segregation and pinhole formation were observed in the atomic force microscopy images of the copolymer film. The ultra-thin copolymer film showed an extremely low leakage current density (J < 10−9 A/cm2 in the range of ±2 MV/cm) even with a 70 nm thickness. Pentacene organic thin-film transistors (OTFTs) were fabricated with the copolymer gate insulator and showed excellent operational stability. An up to 95% initial drain current was maintained, and a negligible shift in threshold voltage (VT) was observed even after applying a constant gate bias stress of −12 V and a corresponding electric field of 1.7 MV/cm to the OTFT for 3 ks.

RF and DC Analysis of Stressed InGaAs MOSFETs

A complete reliability study of the DC and RF characteristics for InGaAs nMOSFETs with Al2O3/HfO2 dielectric is presented. The main stress variation at high frequencies is related to a threshold voltage shift, whereas no decrease is found in the maximum of the cutoff frequency and RF transconductance. Constant gate stress leads to a charge build up causing a threshold voltage shift. Furthermore, electron trapping at the drain side degrades the performance after hot carrier stress. The maximum DC transconductance is reduced following constant gate bias stress, by an increase in charge trapping at border defects. These border defects at the channel/high-κ interface are filled by cold carrier trapping when the transistor is turned on, whereas they do not respond at high frequencies.

Degradation characteristics of high-voltage AlGaN/GaN-on-Si heterostructure FETs under a reverse gate bias stress

We have performed reverse gate bias stress tests on field-plated AlGaN/GaN heterostructure field-effect transistors (HFETs) on Si substrates with high breakdown voltage. The source-to-drain breakdown voltages measured under off-state conditions ranged from 615 to 816 V. However, a sudden increase in the gate leakage current was observed at a critical voltage in the range of 20–30 V during the reverse gate bias stress test with the source and the drain grounded. Two-terminal stress tests were performed on drain-gate and source-gate Schottky diodes, respectively. The reverse leakage currents of both diodes were increased although one electrode was floated during the stress test. This suggests that the defects generated by the stress-induced inverse piezoelectric effect provide a leakage path from the gate contact to the electron channel. The increase in the leakage depended on the location of peak electric field during the stress test. A time-dependent element of the degradation was also observed during the constant gate bias stress test at the critical voltage.

Bias-Stress-Induced Instabilities in P-Type ${\rm Cu}_{2}{\rm O}$ Thin-Film Transistors

We investigate the gate bias-stress-induced instabilities of p-type copper oxide $({\rm Cu}_{2}{\rm O})$ thin-film transistors (TFTs). Transfer curves measured before and after the application of constant gate bias stress under air and vacuum environments show that the partial pressure of the oxygen in the environment does not much affect the transfer characteristics and bias-stress-induced instabilities of the ${\rm Cu}_{2}{\rm O}$ TFTs. During the negative gate bias stresses, the transfer curves shift to the negative direction without a significant variation of the shape, which is attributed to the hole trapping in the interface or bulk dielectric layers with a negligible creation of additional interface trap states. During the positive gate bias stresses, a threshold voltage hardly moves to the positive direction because of the lack of free electron inside the p-type ${\rm Cu}_{2}{\rm O}$ , but a notable degradation of the subthreshold slope is observed. From the recovery characteristics, the generated traps during the positive gate bias stress are estimated to be metastable ones in p-type ${\rm Cu}_{2}{\rm O}$ TFTs.

Anomalous Stress-Induced Hump Effects in Amorphous Indium Gallium Zinc Oxide TFTs

In this paper, we investigated the anomalous hump in the bottom gate staggered a-IGZO TFTs. During the positive bias stress, a positive threshold voltage shift was observed in the transfer curve and an anomalous hump occurred as the stress time increased. The hump became more serious in higher gate bias stress while it was not observed under the negative bias stress. The analysis of constant gate bias stress indicated that the anomalous hump was influenced by the migration of positively charged mobile interstitial zinc ion towards the top side of the a-IGZO channel layer.

Characterization of Border Trap Density With the Multifrequency Charge Pumping Technique in Dual-Layer Gate Oxide

The multifrequency charge pumping (MFCP) experiments have been investigated by many research groups for the characterization of oxide traps in high-permittivity (high-κ ) dielectric metal-oxide-semiconductor field-effect transistor samples. In these previous studies, the duty cycle was changed for control of charging and discharging depths. In this paper, the spatial and energy distributions of border traps in the metal gate/high-κ dielectric/silicon dioxide (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) interfacial layer stack structure were characterized as a three-dimensional (3-D) mesh profile by using the MFCP technique. The presented MFCP technique was based on the frequency of the gate pulse in conjunction with the tunneling model of trapped charges and was not the duty cycle. The methodological basis and the accurate model were introduced for the analysis of the measured MFCP data in dual-layer gate oxide. The low-frequency noise measurement and the MFCP technique were used for the analysis of the constant gate bias stress induced trap generation, and the 3-D mesh profile of generating trap density was presented. Moreover, the energy distribution of stress-induced traps was investigated within high-κ, SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and high-κ/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface.

Modified Threshold Voltage Shift Model in a-Si:H TFTs Under Prolonged Gate Pulse Stress

The threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) instability of hydrogenated amorphous silicon thin film transistor under constant gate bias stress has been examined and modeled as a stretched-exponential equation previously. However, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> shift (Delta V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) characteristic under prolonged gate pulsed stress, which also occurs in practical circuit operation, has not been well modeled so far. In this letter, we compared the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> shift property with existing models under gate pulse stress. For Delta V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> under prolonged stress, we found inaccuracies in the previous models and subsequently proposed a modified model, which can be applied to estimate V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> shift correctly for prolonged pulse stress of various duty ratios.