Configurable Ring Oscillator Physical Unclonable Function Research Articles

A lightweight key renewal scheme based authentication protocol with configurable RO PUF for clustered sensor networks

In clustered sensor networks, an adversary can easily capture and damage a member node. Therefore, it is important to detect the compromised nodes and renew the keys of all other nodes. Although many key renewal schemes have been proposed, the detection of compromised nodes is still difficult to achieve. Furthermore, due to the resources limitation, conventional encryption and authentication protocols are impractical when we take the power consumption and resource usage into consideration. In this paper, a lightweight and energy-efficient authentication protocol and key renewal scheme for clustered sensor networks was proposed, in which the configurable ring oscillator (CRO) physical unclonable function (PUF) is adopted to enhance the security. Typical CRO PUFs, including multiplexer (MUX) based PUF and XOR gate based CRO PUF, are analyzed and compared. The proposed scheme is implemented and evaluated on Zynq 7000 series SoC FPGAs. The results indicate that the configurable PUF structure is cost efficient and the proposed protocol is secure against major attacks on clustered sensor networks.

Research and design of a high-security configurable RO-PUF based on FPGA

Abstract Aiming at the lack of reliability and uniqueness of the traditional configurable ring oscillator physical unclonable function (RO-PUF) due to the simple configurable path, a configurable RO-PUF is proposed based on the delay characteristics of the ring oscillator. The design scheme redesigned the RO structure, making the configurable path of the RO-PUF more flexible and increasing the number of incentive response pairs (CRPs); At the same time, the introduction of a lightweight SPONGENT hash algorithm in the RO-PUF structure makes the mapping between incentives and responses more complicated, prevents attackers from building model attacks by acquiring CRPs, and enhances RO-PUF security. And then, the design scheme is implemented on Xilinx’s Spartan series FPGA chip, and the experimental results are compared and analyzed. The results show that the configurable RO-PUF designed with this scheme has an average reliability of 98.87% and uniqueness of 49.13%.

Design Principles for a Novel Lightweight Configurable PUF Using a Reconfigurable FET

This article presents a mixed signal-based novel configurable ring oscillator (CRO) physical unclonable function (PUF) architecture for resource constrained Internet of Things (IoT) devices. PUF can protect the IoT devices through their unique inherited fingerprints obtained from the manufacture variations. However, the conventional ring oscillator (RO) PUF need multiple replicas of ROs to produce a large set of challenge response pairs (CRPs) which invalidates its usage in an IoT environment. Using the concept of reconfigurable hetero material hetero dielectric FET (HM-HD-RFET) proposed in this manuscript, we have designed a novel CRO which allows 512 challenges and a sigma delta analog to digital converter (ADC) at the end generates a stream of response bits. HM-HD-RFET can be configured into four different combinations of transistors through two polarity gates (PGs) and their switching can be controlled using a control gate (CG). Next, we compare HM-HD-RFET with configurable silicon FET (Si-RFET) and homogenous dielectric FET (HM-RFET) to show that the proposed device performs well in all of the four configurations with negligible ambipolarity. The device characteristics is realized in Silvaco Atlas tool, circuit implementation is done in Cadence using Verilog-A based look table approach and properties of CRO PUF are computed in MATLAB.

Lightweight Configurable Ring Oscillator PUF Based on RRAM/CMOS Hybrid Circuits

Physical unclonable function (PUF) is a lightweight security primitive for energy constrained digital systems. As an enhanced design of conventional ring oscillator (RO) PUFs, configurable ring oscillator (CRO) PUFs improve the uniqueness and reliability compared with the conventional RO PUF designs. In typical CRO PUF designs, multiplexers (MUXs) are utilized as configurable components. In this paper, a hybrid nano-scale CRO ( $hn$ -CRO) PUF is proposed. The configurable components of the proposed $hn$ -CRO PUF are implemented by RRAMs. The delay elements are based on CMOS inverters. Compared with traditional CRO PUF designs, the proposed $hn$ -CRO PUF is cost-efficient in terms of circuit density and gate per challenge response pair (CRP) bit. To validate the proposed $hn$ -CRO PUF, the Monte Carlo simulation results of a compact RRAM model under UMC 65 nm technology are presented. The results show that the proposed $hn$ -CRO PUF has a good uniqueness and low hardware consumption compared with the previous works.

A novel configurable ring oscillator PUF with improved reliability using reduced supply voltage

Out of several delay based Physical Unclonable Functions (PUF), Configurable Ring oscillator (CRO) PUF is a preferred security primitive because of its higher reliability, area efficient CRO section and low power consumption features. The reliability degradation occurs mainly due to temperature variation and aging. Although conventional CRO PUF is highly reliable against temperature variation but it shows less resilient to aging. In this paper, we propose two modified CRO PUF architectures for better reliability against aging related issues. The first architecture uses reduced supply voltage approach to minimize the reliability degradation due to both temperature variation and aging. The second architecture uses a response dependent supply voltage controller approach to prevent reliability degradation by restoring the initial logic level of responses. Both the proposed modified CRO PUF architectures are power efficient than the conventional CRO PUF. Further, the use of single row of cascaded inverter as CRO made both the proposed architectures area efficient than conventional CRO PUF. The performance analysis is carried out in 90 nm CMOS technology. Simulation result confirms improvements in reliability along with low power feature for both the proposed modified CRO PUF.

A novel current controlled configurable RO PUF with improved security metrics

Physical Unclonable Functions (PUFs) are promising hardware security primitives which produce unique signatures. Out of several delay based PUF circuits, Configurable Ring Oscillator (CRO) PUF has got higher uniqueness and it is resilient against modelling attacks. In this paper, we present a novel Current controlled CRO (C-CRO) PUF in which inverters of RO uses different logic styles: static CMOS and Feedthrough logic (FTL). Use of different logic styles facilitates improvement of security metrics of PUF. The analysis of security metrics of the proposed architecture is carried out in 90nm CMOS technology shows, using FTL logic leads to better security metrics. Proposed C-CRO PUF is also both power and area efficient. Further, in order to measure the vulnerability of proposed PUF, machine learning attack is carried out and the result shows FTL RO based C-CRO PUF is highly resilient to machine learning attack because of its non-linearity property.