Conditional Branch Instructions Research Articles

Towards the Improvement of Branch Instructions Identification in High- Performance Processors: Issues, Challenges and Techniques

Introduction: Accurate branch prediction technique has become compulsory in the superscalar and deep pipeline processors. The conditional instructions can break the continuous flow of execution in the pipeline stages, thereby decreasing processor performance. Discussion: This paper highlights the concept of branch prediction, some issues and challenges, and techniques for improving processor performance. Further, this paper also presents the role of branch prediction in different processors and their features. Conclusion: The concept of the branch prediction used in parallel processors to enhance the execution speed of the conditional branch instructions and improve the processor's performance is highlighted in this paper. Further, this paper highlights the branch predictor techniques with their features and presents the challenges, issues, and future techniques related to the branch prediction.

A Hybrid Branch Prediction Approach For High-Performance Processors

Background: In a parallel processor, the pipeline cannot fetch the conditional instructions with the next clock cycle, leading to a pipeline stall. Therefore, conditional instructions create a problem in the pipeline because the proper path can only be known after the branch execution. To accurately predict branches, a significant predictor is proposed for the prediction of the conditional branch instruction. Method: In this paper, a single branch prediction and a correlation branch prediction scheme are applied to the different trace files by using the concept of saturating counters. Further, a hybrid branch prediction scheme is proposed, which uses both global and local branch information, providing more accuracy than the single and correlation branch prediction schemes. Results: Firstly, a single branch prediction and correlation branch prediction technique are applied to the trace files using saturating counters. By comparison, it can be observed that a correlation branch prediction technique provides better results by enhancing the accuracy rate of 2.25% than the simple branch prediction. Further, a hybrid branch prediction scheme is proposed, which uses both global and local branch information, providing more accuracy than the single and correlation branch prediction schemes. The results suggest that the proposed hybrid branch prediction schemes provide an increased accuracy rate of 3.68% and 1.43% than single branch prediction and correlation branch prediction. Conclusion: The proposed hybrid branch prediction scheme gives a lower misprediction rate and higher accuracy rate than the simple branch prediction scheme and correlation branch prediction scheme.

Implementation and comparison of bi-modal dynamic branch prediction with static branch prediction schemes

In a parallel processor, the pipeline cannot fetch the conditional instructions with the next clock cycle, leading to a pipeline stall. So, conditional instructions create a problem in the pipeline because the proper path can only be known after the branch execution. To accurately predict branches, a significant predictor is proposed for the prediction of the conditional branch instruction. Firstly, the always taken prediction scheme and always not-taken prediction scheme are applied to the trace files using a static branch prediction scheme. Further, a bi-modal dynamic branch prediction scheme is proposed, which uses the saturating counter to provide more accuracy rate than the other prediction schemes. The result suggests that the proposed bi-modal dynamic branch prediction scheme provides a higher accuracy rate than always taken and always not-taken static branch prediction by the rate of 9.82% and 6.12%, respectively. Moreover, the proposed bi-modal dynamic branch prediction limits the misprediction rate by 10.33% and 8.16% compared with the always taken and always not-taken static branch prediction scheme.

An Aggressive Implementation Method of Branch Instruction Prefetch

Due to the demand in the field of industrial control, we developed a CPU core based on ARMv8m architecture [1], named TS400, and its performance is comparable to Arm Cortex-M33 [2]. The TS400 has four stages of pipelining, thus having a higher clock frequency than Cortex-M33 which has three stages. With the increase of pipeline stages, extra idle clock beats will be introduced when the pipeline is flushed, which will increase the clock cycles per instruction (CPI) value and decrease the score of CoreMark. Accurate instruction fetch and branch prediction can effectively reduce the impact of refreshing pipeline, at the cost of extra logic resources. In TS400, an aggressive branch instruction prefetch method is designed. Compared with branch prediction technology, this method does not need complex branch prediction logic and is suitable for the design of embedded CPU. The aggressive branch instruction prefetch method includes: 1) reducing the time cost of conditional branch target fetching to the minimum by taking the branch first and then confirming the branch taking result; 2) optimizing the bus control signal timing of the prefetch instruction to make the target address prefetch respond in time. The aggressive branch prefetch method reduces the impact of pipeline stall caused by the execution of conditional branch instructions as much as possible, thus achieving better running performance than Cortex-M33 at the same clock frequency, while the clock frequency performance is superior to Cortex-M33.

DESIGN AND FPGA BASED IMPLEMENTATION OF 1-BIT DYNAMIC BRANCH PREDICTOR FOR THE PARALLELISM PROCESSOR

To improve the performance of the processors, the pipeline technique is used extensively to implement I.L.P (Instruction Level Parallelism). We measure the processor performance through the quantity of Instructions Level Parallelism represented through its design. We can counterstrike the parallelism with the aid of the execution of conditional branch instructions, which might additionally break the flow of the program execution. To overcome the branch problem, numerous ways have been suggested proactive to predict both the direction as well as the address of the executed instructions. In this paper, the FPGA ( Field Programmable Gate Arrays) based implementation of the 1-bit dynamic branch predictor is presented. The 1-bit dynamic branch predictor is developed especially for conditional branch instructions. The pipeline would not detach from the instruction queue when any conditional instructions occur as a 1-bit dynamic branch predictor implements it. This technique improves processor performance by implementing a deduction in the controlling hazard in the pipeline. Modelsim and Quartus tool is used for the design and implementation of the predictor.

Selective branch prediction schemes based on FPGA MIPS processor for educational purposes

Processor performance is measured by amount of ILP (Instruction Level Parallelism) represented by its design. this parallelism is limited by the execution of conditional branch instructions which may break the flow of the program execution. To overcome this problem, several ways were suggested in order to predict both the direction of instructions execution and the address of the instruction to be executed next. In this paper, a design for a dynamic branch predictor was implemented in VHDL (VHSIC Hardware Description Language) then it was integrated with FPGA (Field Programmable Gate Arrays) MIPS (Microprocessor without Interlocked Pipelined Stages) processor and its ability to increase prediction accuracy and MIPS processor performance was approved. This predictor combines gshare and bimodal branch prediction techniques by dividing the PHT (Pattern History Table) into two branch streams corresponding to taken and not-taken states. This combined branch predictor was synthesized using the XILINX ISE (Integrated Software Environment) Design Suite 14.7 tool.

BranchScope

We present BranchScope - a new side-channel attack where the attacker infers the direction of an arbitrary conditional branch instruction in a victim program by manipulating the shared directional branch predictor. The directional component of the branch predictor stores the prediction on a given branch (taken or not-taken) and is a different component from the branch target buffer (BTB) attacked by previous work. BranchScope is the first fine-grained attack on the directional branch predictor, expanding our understanding of the side channel vulnerability of the branch prediction unit. Our attack targets complex hybrid branch predictors with unknown organization. We demonstrate how an attacker can force these predictors to switch to a simple 1-level mode to simplify the direction recovery. We carry out BranchScope on several recent Intel CPUs and also demonstrate the attack against an SGX enclave.

Byte-code scheduling of Java programs with branches for desktop grid

A method for an introductory optimization of multithreaded Java programs for execution on clusters of Java Virtual Machines (JVMs) inside desktop grids is presented. It is composed of two stages. In the first stage, a clustering algorithm is applied to extended macro data flow graphs generated on the basis of the byte-code compiled for multithreaded Java programs. These graphs account for data and control dependencies in programs including conditional branch instructions annotated by branch statistics driven from execution traces for representative sets of data. In the second stage, a list scheduling is performed based on the Earliest Task First (ETF) heuristics in which node mapping on JVMs accounts for mutually exclusive paths outgoing from conditional branch nodes. The presented object placement optimization algorithm is a part of the DG-ADAJ environment.

Three control flow obfuscation methods for Java software

Three novel control computation (control flow) obfuscation methods are described for protecting Java class files. They are basic block fission obfuscation, intersecting loop obfuscation and replacing goto obfuscation. The basic block fission obfuscation splits some chosen basic block(s) into more basic blocks, in which opaque predicates and goto instructions are inserted to make decompiling unsuccessful. The intersecting loop obfuscation intersects two loops and then adds this pattern into programs. The intersecting loop structure should not appear in a Java source program or a class file. The replacing goto obfuscation replaces goto instructions with conditional branch instructions. The new methods were tested against 16 decompilers. The study also implemented multi-level exit obfuscation and single-level exit obfuscation for comparison. Both the intersecting loop obfuscation and the replacing goto obfuscation successfully defeated all the decompilers.

An Embedded RISC Core Performance for ATM Network Interface Processing

The use of an embedded reduced instruction set computer (RISC) as a processing core for an ATM network interface can provide such interface with very useful features, such as simplicity of interface design, short developing cycle, and reduced cost of development. In addition, it provides scalability where such core could support the processing requirements by ATM interface to deliver different high-speed data transmission, which the user-network ATM interface protocol recommends. This article describes a VHDL-based simulation study we have conducted to investigate the RISC core design issues for high-speed scalable ATM host-network interface. The simulation results have shown that the three-stage pipeline RISC core supported with forwarding mechanism and delayed branch technique can process all the ATM interface codes without performance penalty due to the read-after-write data hazards and conditional branch processing. The core should be supported, however, with a forwarding mechanism to eliminate the stalling of the pipeline due to the processing of the conditional branch instructions. Also, the core structure should include a content addressable memory and direct memory access and support a simple instruction set. Also, the results show that a cost-effective RISC core could support a wide range of ATM user-network speeds.

The program decision logic approach to predicated execution

Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the major impediments to achieving this goal has been inefficient programmatic control flow. Historically, the compiler has translated the programmer's original control structure directly into assembly code with conditional branch instructions. Eliminating inefficiencies in handling branch instructions and exploiting ILP has been the subject of much research. However, traditional branch handling techniques cannot significantly alter the program's inherent control structure. The advent of predication as a program control representation has enabled compilers to manipulate control in a form more closely related to the underlying program logic. This work takes full advantage of the predication paradigm by abstracting the program control flow into a logical form referred to as a program decision logic network. This network is modeled as a Boolean equation and minimized using modified versions of logic synthesis techniques. After minimization, the more efficient version of the program's original control flow is re-expressed in predicated code. Furthermore, this paper proposes extensions to the HPL PlayDoh predication model in support of more effective predicate decision logic network minimization. Finally, this paper shows the ability of the mechanisms presented to overcome limits on ILP previously imposed by rigid program control structure.

Evaluating the Cost of conditional branches on the performance of superscalar machines

This paper presents a study of the impact of conditional branch instructions on the performance of Superscalar processors. By interpreting non-optimised code of a real processor on various configurations derived from a Superscalar architecture model, we have evaluated the execution time percentages in which the associative dispatch algorithm remains idle, waiting for the completion of conditional branch instructions. In addition, we have assessed the volume of instruction level parallelism that can be extracted from application programs if the target machine is equipped with an omniscient branch predictor.

Effect of prediction accuracy on the performance of an instruction pipeline

A general weakness of instruction pipelines is ‘bubbles’ or ‘holes’ in the pipeline due to conditional branch instructions. Most of the solutions (Lee and Smith 1984) to the branch problem attempt to predict whether or not a branch will be taken. If the prediction is correct, then the correct sequence of instructions can be initiated without delay. The performance of an instruction pipeline is analyzed to give a measure of the efficiency or utilisation of the pipeline segments in terms of the probability of correct branch prediction (referred to as the prediction accuracy). The analysis is based on the space-time relationship. The performance of an instruction pipeline with both equal and unequal segment times is analysed incorporating the effect of two types of conditional branch instructions in the instruction sets of computers. The results of the analysis enable one to study the sensitivity of the performance of an instruction pipeline to the number of conditional branch instructions and the probabilit...

Performance Analysis of Pipeline Architecture

Pipelining has emerged asa powerful technique for obtaining a high throughput rate. The paper analyses Pipeline Architecture reviewing many problems of Instruction Pipeline. The measure of effectiveness in executing a job on a pipelined processor is given by efficiency deduced from the space-time relationship. An expression for efficiency has been deduced when segment times are unequal.Performance of Instruction Pipeline suffers when conditional branch instructions are present in a programme. An expression has been deduced relating efficiency with the number of procedural dependencies in a programme. The suitability of the programme for execution on a pipelined processor may be determined by dynamic measurement of instruction frequencies as suggested here.