Concurrent State Machines Research Articles

Parallelism in Autonomous Robotic Surgery

Robots can perform multiple tasks in parallel. This work is about leveraging this capability in automating multilateral surgical subtasks. In particular, we explore, in a simulation study, the benefits of considering this parallelism capability in developing execution models for autonomous robotic surgery. We apply our work to two surgical subtask categories: (i) coupled-motion subtasks, where multiple robot arms share the same resources to perform the subtask, and (ii) decoupled-motion subtasks, where each robot arm executes its part of the task independently from the others. We propose and develop parallel execution models for the surgical debridement subtask, a representative of the first category, and the multi-throw suturing subtask, a representative of the second one. Comparing these parallel execution models to the state-of-the-art ones shows significant reductions in the subtasks completion time by at least 40%. In 20 trials, our results show that our proposed model for the surgical debridement subtask, that uses hierarchical concurrent state machines, provides a parallel execution framework that is efficient while greatly reducing collisions between the arms compared to a naive parallel execution model without coordination. We also show how applying parallelism can lead to execution models that go beyond the normal practice of human surgeons. We finally propose the notion of “automation for surgical manual execution” where we argue that autonomous robotic surgery research can be used as a tool for surgeons to discover novel manual execution models that can significantly improve their surgical practice.

BSP abstract state machines capture bulk synchronous parallel computations

The bulk synchronous parallel (BSP) bridging model is a model for concurrent computations with alternating computation and communication phases between programs running on different processors. In a computation phase the programs proceed independently and asynchronously until a barrier is reached. In a communication phase initiated by all programs having reached the barrier only messages between the programs are exchanged until normal processing can be continued. In this article we present a behavioural theory for BSP computations comprising an axiomatisation of the BSP model, the definition of a restricted class of concurrent abstract state machines, which we call BSP abstract state machines, and the proof that BSP abstract state machines capture BSP computations as defined by the axiomatisation. We illustrate the use of BSP abstract state machines on map-reduce. • Language-independent axiomatisation of the BSP bridging model. • Proof that only from the axiomatisation the alternation of computation and communication phases can be obtained. • Definition of BSP-ASMs. • Proof that BSP-ASMs capture BSP algorithms as defined by the axiomatisation.

Formal Analysis of Virtual Machine Migration and Identification of Faults

Infrastructure as a service (IaaS) cloud supports flexible and agile execution of applications by creating virtualized execution environment namely, virtual machines (VMs) with on-demand infrastructural resources. In such environment, VM migration is used as a tool to facilitate system maintenance, load balancing and fault tolerance. The use of VM migration is to establish the portfolio of using dynamic and scalable infrastructure services offered by the service providers. In this paper, we study the VM migration process and investigate the potential faults which can occur during migration. Also, the state changes of a VM throughout its lifetime has been systematically analyzed and modeled as concurrent state machines. The potential faults are presented considering the live migration process of VM and accordingly VM state changes. In addition, a methodology for identifying the migration faults has been presented.

Reverse engineering concurrent UML state machines using black box testing and genetic programming

This paper presents a technique for reverse engineering, a software system generated from a concurrent unified modeling language state machine implementation. In its first step, a primitive sequential finite-state machine (FSM) is deduced from a sequence of outputs emitted from black box tests applied to the systems’ input interface. Next, we provide an algorithmic technique for decomposing the sequential primitive FSM into a set of concurrent (orthogonal) primitive FSMs. Lastly, we show a genetic programming machine learning technique for discovering local variables, actions performed on local and non-binary output variables, and two types of intra-FSM loops, called counting-loops and while-loops.

Concurrent abstract state machines

A concurrent Abstract State Machine (ASM) is a family of agents each equipped with a sequential ASM to execute. We define the semantics of concurrent ASMs by concurrent ASM runs which overcome the problems of Gurevich's distributed ASM runs and generalize Lamport's sequentially consistent runs. A postulate characterizing an intuitive understanding of concurrency is formulated. It allows us to state and prove an extension of the sequential ASM thesis to a concurrent ASM thesis.

An efficient hybrid approach to per-flow state tracking for high-speed networks

Maintaining per-flow information and state is a crucial topic in network monitoring. Tracking per-flow state is a relatively new area. Two main approaches have been proposed for tracking state: Binned Duration Flow Tracking (BDFT) and Fingerprint-Compressed Filter Approximate Concurrent State Machine (FCF ACSM). BDFT which uses Bloom filters is time efficient, whereas FCF ACSM using d-left hash tables has near-perfect memory efficiency but has higher computational cost. This paper presents a hybrid method (BDFT-H) by employing the best features of BDFT and FCF ACSM to achieve both time and space efficiency. Performance analysis and comparisons are conducted for BDFT, FCF ACSM, and BDFT-H. These methods are all intended for implementation on high-speed routers where resources such as memory and CPU time are limited. For the computational performance of the three schemes, we find that based on analysis, d-left hashing may require substantially more computational resources than Bloom filters. We also conduct simulations to compare the accuracy of these three schemes and the results show that all three methods can achieve over 99% accuracy on traces of real traffic. The proposed BDFT-H provides the best overall tradeoff between time and space efficiency. Both BDFT and FCF ACSM may have the false positive issue. This paper also presents two additional BDFT extensions: BDFT-FPR (false positive removal) and BDFT-FPC (false positive correction) to deal with the false positive issue. Performance comparisons for BDFT and these two BDFT extensions are also conducted using real traffic traces for comparison.

The development of a hardware- and software-based simulation platform for the training of driver candidates

In this study, a traffic simulation system (TSS) to provide novice driver candidates with opportunities for training and testing has been developed. Autonomous vehicles that follow the flow of traffic in a microsimulation environment were prepared using a hierarchical concurrent state machine. Autonomous vehicles are skilled and have behavioral aspects such as tracking the lanes, following the vehicles, complying with traffic rules, decelerating, accelerating, and intersection crossings. These driver behaviors are parameterized to allow the autonomous agents to act while disregarding the rules (i.e. aggressive behaviors) or behaving normally. The TSS is operated in 3 different modes, namely the orientation, training, and testing modes. During the orientation phase, the candidate driver's target is to get used to the system and the vehicle, along with traffic rules in city conditions. During training, the driver is warned orally (when necessary) and given written handouts about the mistakes that occurred during the training session. The rules to be obeyed in traffic are kept in an XML file in the system and the data are used to follow the driver's behaviors. During the testing phase, an evaluation mechanism is employed. It observes whether the drivers obey or disregard the rules during the testing time interval. At the end of the test drive, a report showing the driver's mistakes is given. The reports and test results can be recorded in the database with the drivers' names for further analysis and evaluation processes. Driver candidates perform the driving using a steering wheel and pedals, along with a screen platform consisting of 3 monitors. With the TSS user interface, parameterized items such as vehicle selection, the crowdedness of the traffic, the timing of the traffic lights, and the determination of air conditions are possible. The system provides a cheap, affordable, and nonrisky platform for the trainees. Test results show that the system improves the drivers' skills and builds trust in them.

Petri Net Based Specification in the Design of Logic Controllers with Exception Handling Mechanism

Petri Net Based Specification in the Design of Logic Controllers with Exception Handling Mechanism Hierarchical Petri nets beside UML state machine diagrams, sequentional function charts (SFC) and hierarchical concurrent state machines are common solution for specification of logic controllers. These specification formats provide both concurrency and modeling on multi levels of abstraction (hierarchic approach). But only state machine diagrams supports exceptions handling in direct way. Program model presented in form of state machine diagram may be later transformed into a program in the SFC language or transformed in the Petri Net and implemented in the FPGA structure. Similarity between SFC language and Petri Nets give us lot of tools for analysis such control system. Article presents new approach for exceptions handling in hierarchical Petri nets as formal specification for logic controllers. Proposed method of specification can be used independently or as a part of dual specification (correlated state machine diagram and hierarchical configurable Petri Net).

A new driver behavior model to create realistic urban traffic environment

Abstract This paper presents a new driver behavior model, which emulates various driving styles (i.e. behaviors) for different categories of drivers. The model was highly parametric and was developed based on a two-layer Hierarchical Concurrent State Machines (HCSM) programming framework. Our study has been specifically oriented to create a realistic urban traffic environment with hazardous situations typical of real life in a driving simulator, and let the novice drivers to practice in a safe environment. In our study, we used TRAFIKENT driving simulator as a test-bed. Experiments and evaluations demonstrated satisfactory results in terms of behavioral validity of our model.

FORMAL REASONING IN LOGIC DESIGN OF RECONFIGURABLE CONTROLLERS

The rigorous digital design of embedded Reconfigurable Logic Controller starts from hierarchical concurrent state machine model (HCSM), which has been formally derived from modular control interpreted Petri net. The colored tokens, arcs, places and transitions distinguish nested State Machine Modules. Colored coordination places, called doubles facilitate effective and flexible Petri net state encoding. The rule based on a textual logic description of the Petri net is accepted by the hardware description language VHDL and easily mapped into Field Programmable Gate Array macrocells. Several combinatorial procedures in formal digital design of logic controller are supported by formal reasoning in the monotone Gentzen calculus.

Predecessor existence problems for finite discrete dynamical systems

We study the predecessor existence problem for finite discrete dynamical systems. Given a finite discrete dynamical system S and a configuration C , the Predecessor existence (or Pre) problem is to determine whether there is a configuration C ′ such that S has a transition from C ′ to C . In addition to the decision version, we also study the following variants: the #-Predecessor existence (or #Pre) problem–counting the number of predecessors, the Unique-Predecessor existence (or UPre) problem–deciding whether there is a unique predecessor and the Ambiguous-Predecessor existence (or APre) problem–given a configuration C and a predecessor C ′ of C , deciding whether there is a different predecessor C ″ of C . General techniques are presented for simultaneously characterizing the computational complexity of the Pre problem and its three variants. Our hardness results are based on the concept of simultaneous reductions: single transformations that can be used to simultaneously prove the hardness of the different variants of the Pre problem for their respective complexity classes. Our easiness results are based on dynamic programming and they extend the previous results on Pre problem for one-dimensional cellular automata. The hardness results together with the easiness results provide a tight separation between easy and hard instances. Further, the results imply similar bounds for other classes of finite discrete dynamical systems including discrete Hopfield and recurrent neural networks, concurrent state machines, systolic networks and one- and two-dimensional cellular automata. Our results extend the earlier results of Green, Sutner and Orponen on the complexity of the predecessor existence problem and its variants.

Code Generation For Csm/Ecsm Models In Cosma Environment

The COSMA software environment, developed in the Institute of Computer Science, WUT,was designed primarily for model checking of reactive systems specified in terms of ConcurrentState Machines (CSM). However, COSMA supports also Extended CSM (ECSM).The extensions allow for using complex data types and pieces of C/C++ code, attributedto CSM states and/or transitions. Because of these extensions, ECSM models cannot beverified by model checking, but they can be used as an intermediate step in code generation.The underlying CSM represent then the flow of control within cooperating components andthe communication among them while the extensions specify the data structures and thedetails of their processing.The paper discusses the code generation from ECSM diagrams. The approach is illustratedwith an example.

TIMED CONCURRENT STATE MACHINES

Timed Concurrent State Machines are an application of Alur Timed Automata concept tocoincidence-based (rather than interleaving) CSM modeling technique. TCSM support theidea of testing automata, allowing to specify time properties easier than temporal formulas.Also, calculation of a global state space in real-time domain (Region Concurrent State Machines)is defined, allowing to store a verified system in ready-to-verification form, and tomultiply it by various testing automata.

Beyond bloom filters

Many networking applications require fast state lookups in a concurrent state machine,which tracks the state of a large number of flows simultaneously.We consider the question of how to compactly represent such concurrent state machines. To achieve compactness,we consider data structures for Approximate Concurrent State Machines (ACSMs)that can return false positives,false negatives,or a "don 't know "response.We describe three techniques based on Bloom filters and hashing,and evaluate them using both theoretical analysis and simulation.Our analysis leads us to an extremely efficient hashing-based scheme with several parameters that can be chosen to trade off space,computation,and the pact of errors.Our hashing approach also yields a simple alternative structure with the same functionality as a counting Bloom filter that uses much less space.We show how ACSMs can be used for video congestion control.Using an ACSM,a router can implement sophisticated Active Queue Management (AQM)techniques for video traffic (without the need for standards changes to mark packets or change video formats),with a factor of four reduction in memory compared to full-state schemes and with very little error.We also show that ACSMs show promise for real-time detection of P2P traffic.

Heuristic algorithm for an effective state encoding for reconfigurable matrix - based logic controller design

Abstract The paper presents the new effective version of heuristic algorithm for state assignment of concurrent finite state machines. The algorithm is devoted for effective, rapid local state encoding, during an implementation of logic controller programs, specified in Structured Text (ST) - taken from international standard IEC 1131-3. It is considered that textual specification in ST is closely related with an equivalent Sequential function Chart SFC. For the sake of simplicity the slightly restricted sound SFC is treated as a standardised version of control interpreted Petri Net. The obtained state encoding is especially suited and useful for a compact representation of binary control algorithms.

Emlan: A Language for model checking of embedded systems software

Abstract Embedded System Modelling Language (EMLAN) is high-level, C-like language for modelling and model checking of embedded systems. The language addresses a number of topics concerning embedded systems such as: partitioning of the system, concurrency, interrupts, synchronization mechanisms, time, data transformations hardware interactions. Model checking of the EMLAN specification is based on translations into DT-CSM (Discrete Time Concurrent State Machines), generation of a reachability graph and checking requirements expressed as CTL temporal formulas. The paper presents the EMLAN language, methods of translation into DT-CSM and an example of specification and symbolic verification of the traffic light controller.

Behavioral an real-time verification of a pipeline in the COSMA environment

The case study analyzed in the paper illustrates the example of model checking in the COSMA environment. The system itself is a three-stage pipeline consisting of mutually concurrent modules which also compete for a shared resource. System components are specified in terms of Concurrent State Machines (CSM) The paper shows verification of behavioral properties, model reduction technique, analysis of counter-example and checking of real time properties.

RECONFIGURABLE LOGIC CONTROLLER FOR EMBEDDED APPLICATIONS

The design methodology of modular Logic Controllers, which are realised in reconfigurable array logic, is presented. Sequential Function Chart is considered as an initial behavioural specification of Concurrent State Machine with Data Path. SFC is supplemented with textual explanation of its guards and actions, written in Structured Text. Before a final design, it is transformed into a particular kind of modular control interpreted Petri net and described in VHDL on Register Transfer Level. The dedicated Data Path is formed from previously designed Function Blocks. Refined, structured and verified description of Reconfigurable Logic Controller is mapped directly into FPGA by means of using dedicated and commercial synthesis tools.

Building a system for autonomous aerial robotics research

This paper describes the design of a successfully deployed UAV research platform based on a commercially available radio controlled helicopter. Research is directed towards autonomous aerial robots operating in dynamic outdoor environments. The notion of autonomy is discussed and requirements for the system design are derived. Hierarchical concurrent state machines are used for modeling and realizing a hybrid control system and its interaction with deliberative services. The proposed system allows efficient development and evaluation of control strategies and provides sufficient exibility for studying autonomy.

Inference of message sequence charts

Software designers draw message sequence charts for early modeling of the individual behaviors they expect from the concurrent system under design. Can they be sure that precisely the behaviors they have described are realizable by some implementation of the components of the concurrent system? If so, can we automatically synthesize concurrent state machines realizing the given MSCs? If, on the other hand, other unspecified and possibly unwanted scenarios are "implied" by their MSCs, can the software designer be automatically warned and provided the implied MSCs? In this paper, we provide a framework in which all these questions are answered positively. We first describe the formal framework within which one can derive implied MSCs and then provide polynomial-time algorithms for implication, realizability, and synthesis.