Concurrent Error Detection Systems Research Articles

The Concurrent Error-Detection Systems Organization Based on the Boolean Complement Method with the Preliminary Transformation of Operating Functions into Check Vectors of Berger Codes

The article describes a new way of concurrent error-detection (CED) systems organization using the Boolean complement method, which involves the use of pre-compression of signals from the diagnostic object using encoders of classical sum codes (Berger codes). Control of compressed signals is carried out using the constant-weight "1-out-of-4" code. In comparison with the known methods of the CED systems organization, it is possible to implement a self-checking digital device using one such circuit, and this significantly reduces the structural redundancy. The article suggests using the encoders of modified Berger codes with improved error detection characteristics as a compression scheme.

The Self-Checking Concurrent Error-Detection Systems Synthesis Based on the Boolean Complement to the Bose-Lin Codes with the Modulo Value M=4

The presented paper is devoted to the development of the Boolean complement method for the organization of the self-checking concurrent error-detection (CED) systems for digital devices. The article considers the features of using the modular sum codes (Bose-Lin codes) for these purposes, especially the Bose-Lin code by the modulo M = 4. This code has two check bits and only four different check vectors, this makes it easier to use it in the organization of the self-checking CED system. The article presents the block diagrams of the organization of the CED system by the method of Boolean complement to the considered modular sum code. The examples of the CED system synthesis by the Boolean complement method are given. The article defines the restrictions imposed on the CED systems synthesis procedure, and also forms an algorithm for synthesizing a self-checking CED systems by the method of the Boolean complement to the Bose-Lin code by the modulo M = 4.

КОДЫ БЕРГЕРА В СХЕМАХ ВСТРОЕННОГО КОНТРОЛЯ, РЕАЛИЗОВАННЫХ НА ОСНОВЕ МЕТОДА ЛОГИЧЕСКОГО ДОПОЛНЕНИЯ

The article deals with the previously unknown characteristics of the error detection by using classical Berger codes based on their multiplicities and types (unidirectional, symmetrical and asymmetrical), which can be applied in the concurrent error-detection (CED) systems synthesis, for example, through the use of Boolean complement method. The article shows that Berger codes do not detect a certain amount of both symmetrical, unidirectional and asymmetrical errors in code words. This differs from the previously identified characteristics of the error detection only in data vectors of Berger codes (in this case, any symmetrical errors are not detected, and any unidirectional and asymmetrical errors are detected, which is used in the synthesis of systems with fault detection). The share of undetectable er-rors from their total number for Berger codes with data vector lengths r = 4,…,7 is less than 2%, and for Berger codes with data vector lengths r = 8,…,15 it is less than 0.5%. The use of classical sum codes is effective in the CED systems synthesis, including the Boolean complement method, in which both data and check bits of code words are calculated using the diagnostic object itself

The features of the concurrent error-detection systems of combinational logic circuits based on the search for groups of symmetrically-independent outputs construction

The authors of the article found that in the use of classical sum codes (Berger codes) and a some of their modifications in the combinational circuits testing organization it is possible to detect both unidirectional and part of non-unidirectional errors in the data vectors. It is shown that it is possible to search for such groups of outputs of combinational circuits where only symmetrical errors occur due to stuck at-faults of elements of the internal structure of the circuits. Such groups of outputs are designated as symmetrically-independent outputs (SI-groups of outputs). The conditions of belonging of the group of outputs of the combinational circuits to the SI-groups of outputs are determined. It is shown that each SI-group of outputs can be controlled using a separate testing subsystem based on the code with the detection of any non-symmetrical errors (in particular, and any non-symmetrical errors up to certain multiplicities). The ways of searching for SI-groups of outputs in the combinational circuits testing organization are presented

Sum Codes with Fixed Values of Multiplicities for Detectable Unidirectional and Asymmetrical Errors for Technical Diagnostics of Discrete Systems

We introduce the concept of sum codes with fixed values of the multiplicities of unidirectional and asymmetrical errors in data vectors. We show that such codes can be constructed on the basis of weighing one of the data vector's bits by a natural number w = 2 and then calculating the total weight of the data vector modulo the Berger code (M = 2[log2(m+1)]). We establish the basic characteristics of the new class of sum codes. Compared with the Berger code, the proposed codes have the advantage of detecting symmetrical errors while maintaining the property of detecting any unidirectional and asymmetrical errors up to fixed multiplicities. Such codes can be effectively used in the construction of concurrent error-detection systems for combinational logic devices and, especially, in the construction of systems with the detection of all single faults in the controlled device.

Обнаружение неисправностей в комбинационных схемах на основе самодвойственного дополнения до равновесных кодов

A new method of combinational circuits concurrent checking is considered based on Boolean complement of the working functions of the diagnosis object to the constant-weight code words with parallel checkout of the bits functions belonging to the self-dual functions class of the Boolean logic. The described approach to the organization of concurrent error-detection (CED) systems allows to increase the detection ability in comparison with the traditional checkout by constant-weight code. In this case, the undetectable error can be a such error, which will lead to the preservation of the code word weight generated at the outputs of the Boolean complement block, if the distortions of all the functions bits on the opposite sets is coincide. This condition is more stringent than the checkout of the vector belonging a pre-selected code, it means that it gives a greater probability of detecting distortion arising from errors. The described method allows checkout of combinational circuit based on constant-weight codes with the same number of single and zero bits. In this case, the priority is in the widely used «2-out-of-4» code, which has a simple checker structure. A detailed description of the new CED system structure is given, and algorithms for the extension of definition of the values of the checkout functions that provide testability of technical diagnostic tools are given.

Особенности организации систем функционального контроля комбинационных схем на основе полиномиальных кодов

Objective: To study the specificities of polynomial codes application during the organization of concurrent error detection systems for combinational logic circuits of automation and computer engineering. Methods: The methods of information theory and coding, the theory of discrete devices and diagnostic engineering of discrete systems were applied. Results: The possibilities of using polynomial codes in the process of combinational logic circuits control organization were analyzed. Some essential properties, inherent in generator polynomials, which make it possible to synthesize self-checking circuits of concurrent error detection systems, were pointed out. Particularly, one of such essential properties is the presence of a constant term in a generator polynomial (otherwise, all the required test patterns are not generated for a complete check of a coding device). An example of concurrent error detection sys- tem implementation for a combinational circuit was given. Some experimental data on error detection in LGSynth’89 combinational benchmarks were described. Practical importance: The use of polynomial codes for combinational circuit control makes it possible to synthesize self-checking discrete devices of automation and computer engineering.

Экспериментальные исследования кодов с суммированием единичных и одного взвешенного разрядов в системах функционального контроля

Экспериментальные исследования кодов с суммированием единичных и одного взвешенного разрядов в системах функционального контроля

Sum Codes with Efficient Detection of Twofold Errors for Organization of Concurrent Error-Detection Systems of Logical Devices

Developed were new sum codes detecting efficiently twofold errors in the data vectors. A method of constructing concurrent error-detection systems of the logical combination devices with detection of all single malfunctions based on decomposing the outputs into individual groups and checking them with the use of new sum codes was proposed.

Two-Modulus Codes with Summation of On-Data Bits for Technical Diagnostics of Discrete Systems

A fundamentally new approach to building a code with summation of on-data bits based on the selection and separate check of subsets of bits of the data vector is presented. The properties of the proposed code are analyzed in comparison with the classic and modified Berger codes. The advantages and disadvantages of new codes with summation of on-data bits are noted. The basic properties of the proposed codes with summation that should be taken into account in solving problems of technical diagnostics are established. The results of experimental applications of the developed codes to the organization of concurrent error detection systems of combinational benchmarks from LGSynth`89 are given.

Синтез систем функционального контроля многовыходных комбинационных схем на основе метода логического дополнения

Синтез систем функционального контроля многовыходных комбинационных схем на основе метода логического дополнения

Коды с суммированием с последовательностью весовых коэффициентов, образующей натуральный ряд чисел, в системах функционального контроля

Коды с суммированием с последовательностью весовых коэффициентов, образующей натуральный ряд чисел, в системах функционального контроля

Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger’s code

We formulate necessary and sufficient conditions for detecting a fault at the output of a logical element in a combination logical device in a concurrent error-detection system based on Berger's code. We introduce the notion of a fully testable fault. We show that in order to ensure that all single faults in combination devices are detected with their concurrent checking based on Berger's code we can use not only the property that it detects 100% of unidirectional errors but also the property that it detects 100% of asymmetrical errors. Due to the latter property, we can reduce structural redundancy of the combination device, when transforming its circuit to one amenable for control, compared to known algorithms for modifying the structure of combination devices into circuits with unidirectionally independent outputs.

Метод логического дополнения на основе равновесного кода «1 из 4» для построения полностью самопроверяемых структур систем функционального контроля

Метод логического дополнения на основе равновесного кода «1 из 4» для построения полностью самопроверяемых структур систем функционального контроля

New structures of the concurrent error detection systems for logic circuits

Proposed were new structures for concurrent error detection systems of the combinatorial logic circuits based on the codes with summation of the weighted transitions and their modifications. They were compared with the traditional systems of duplication and check by the Berger code. The structure based on the code with summation of the weighted transitions allowed one to improve the index of realization complexity as compared with the duplication system by 4 % on the average. The structure obtained by modifying the code with summation of the weighted transitions into the optimal code enables one to improve this index almost twice as much as compared with the system of checking by the Berger code. At that, this system has a better index of error detection. In certain cases, the structure of the concurrent error detection system on the basis of the optimal code is superior in complexity to the system of parity check.

Модифицированные коды с суммированием взвешенных переходов в системах функционального контроля комбинационных схем

A method for constructing modified codes with summation of weighted transitions between bits in data vectors occupying neighboring positions is proposed. New codes with summation have the same number of check bits as the classic Berger codes, but they detect more errors in data vectors. Modified codes with summation of weighted transitions in comparison with Berger codes also have improved error detection characteristics in the area of small multiplicity. In addition, for some values of the lengths of information vectors codes can be constructed with the detection of any twofold and any triple errors. The authors developed a method for synthesizing concurrent error detection systems of combinational circuits, based on the analysis of the topology of the object of diagnosis with the selection of groups of checkable outputs, taking into account the properties of error detection by modified codes with summation of weighted transitions. An algorithm for the synthesis of a concurrent error detection systems has been developed.

Построение полностью самопроверяемых структур систем функционального контроля с использованием равновесного кода «1 из 3»

Построение полностью самопроверяемых структур систем функционального контроля с использованием равновесного кода «1 из 3»

Модульные коды с суммированием в системах функционального контроля. I. Свойства обнаружения ошибок кодами в информационных векторах

Модульные коды с суммированием в системах функционального контроля. I. Свойства обнаружения ошибок кодами в информационных векторах

Модульные коды с суммированием в системах функционального контроля. II. Уменьшение структурной избыточности систем функционального контроля

Модульные коды с суммированием в системах функционального контроля. II. Уменьшение структурной избыточности систем функционального контроля

Ways to set up a concurrent error detection system for logical circuits without memory

Classical and modulo codes with summation of active bits of data vectors are often used to set up a concurrent error detection system for logical circuits without memory. Due to specificity in code generation, the number of ways for organizing the concurrent error detection system is equal to the number of inputs of the tested object. The task of expending the set of codes with summation has appeared. Methods of digital device theory, coding theory, and technical diagnostic theory are used for solving this problem. The generalized algorithm for generating the generic class of modulo modified code with summing of the active bits of data vectors is presented and the set’s cardinality is determined for the given number of outputs of the tested object. The essence of the presented class of codes lies in the determination of the smallest nonnegative deductions of a data vector’s weight and correction of the obtained modified weights. Modulo modified codes with summing of the active bits of data vectors are characterized by different properties of error detection in functional diagnostic systems. This makes it possible to generate dependable digital devices with reduced hardware redundancy and power consumption.