Computer Memory Research Articles

Electric-magnetic duality and Z2 symmetry enriched Abelian lattice gauge theory

Kitaev’s quantum double model is a lattice realization of Dijkgraaf–Witten topological quantum field theory. Its topologically protected ground state space has broad applications for topological quantum computation and topological quantum memory. We investigate the Z2 symmetry enriched generalization of the model for the Abelian group in a categorical framework and present an explicit Hamiltonian construction. This model provides a lattice realization of the Z2 symmetry of the topological phase. We discuss in detail the categorical symmetry of the phase, for which the electric-magnetic (EM) duality symmetry is a special case. The aspects of symmetry defects are investigated using the G-crossed unitary braided fusion category. By determining the corresponding anyon condensation, the gapped boundaries and boundary-bulk duality are also investigated. In the last part, an explicit lattice realization of EM duality is discussed.

Development of a novel self-healing Zn(II)-metallohydrogel with wide bandgap semiconducting properties for non-volatile memory device application

A rapid and effective strategy has been devised for the swift development of a Zn(II)-ion-based supramolecular metallohydrogel, termed Zn@PEH, using pentaethylenehexamine as a low molecular weight gelator. This process occurs in an aqueous medium at room temperature and atmospheric pressure. The mechanical strength of the synthesized Zn@PEH metallohydrogel has been assessed through rheological analysis, considering angular frequency and oscillator stress dependencies. Notably, the Zn@PEH metallohydrogel exhibits exceptional self-healing abilities and can bear substantial loads, which have been characterized through thixotropic analysis. Additionally, this metallohydrogel displays injectable properties. The structural arrangement resembling pebbles within the hierarchical network of the supramolecular Zn@PEH metallohydrogel has been explored using FESEM and TEM measurements. EDX elemental mapping has confirmed the primary chemical constituents of the metallohydrogel. The formation mechanism of the metallohydrogel has been analyzed via FT-IR spectroscopy. Furthermore, zinc(II) metallohydrogel (Zn@PEH)-based Schottky diode structure has been fabricated in a lateral metal–semiconductor-metal configuration and it’s charge transport behavior has also been studied. Notably, the zinc(II) metallohydrogel-based resistive random access memory (RRAM) device (Zn@PEH) demonstrates bipolar resistive switching behavior at room temperature. This RRAM device showcases remarkable switching endurance over 1000 consecutive cycles and a high ON/OFF ratio of approximately 270. Further, 2 × 2 crossbar array of the RRAM devices were designed to demonstrate OR and NOT logic circuit operations, which can be extended for performing higher order computing operations. These structures hold promise for applications in non-volatile memory design, neuromorphic and in-memory computing, flexible electronics, and optoelectronic devices due to their straightforward fabrication process, robust resistive switching behavior, and overall system stability.

Representation and computation in visual working memory.

The ability to sustain internal representations of the sensory environment beyond immediate perception is a fundamental requirement of cognitive processing. In recent years, debates regarding the capacity and fidelity of the working memory (WM) system have advanced our understanding of the nature of these representations. In particular, there is growing recognition that WM representations are not merely imperfect copies of a perceived object or event. New experimental tools have revealed that observers possess richer information about the uncertainty in their memories and take advantage of environmental regularities to use limited memory resources optimally. Meanwhile, computational models of visuospatial WM formulated at different levels of implementation have converged on common principles relating capacity to variability and uncertainty. Here we review recent research on human WM from a computational perspective, including the neural mechanisms that support it.

Tricking AI chips into simulating the human brain: A detailed performance analysis

In recent years, significant strides in Artificial Intelligence (AI) have led to various practical applications, primarily centered around training and deployment of deep neural networks (DNNs). These applications, however, require considerable computational resources, predominantly reliant on modern Graphics-Processing Units (GPUs). Yet, the quest for larger and faster DNNs has spurred the creation of specialized AI chips and efficient Machine-Learning (ML) software tools like TensorFlow and PyTorch have been developed for striking a balance between usability and performance. Simultaneously, the field of computational neuroscience shares a similar quest for increased computational power to simulate more extensive and detailed brain models, while also keeping usability high. Although GPUs have also entered this field, programming complexity remains high, resulting in cumbersome simulations. Inspired by AI progress, we introduce a workflow for easily accelerating brain simulations using TensorFlow and evaluate the performance of various, cutting-edge AI chips – including the Graphcore Intelligence-Processing Unit (IPU), GroqChip, Nvidia GPU with Tensor Cores, and Google Tensor-Processing Unit (TPU) – when simulating a biologically detailed as well as simpler brain models. Our model simulations explore the architectural tradeoffs of a modern-day CPU and these four AI platforms by varying computational density, memory requirements and floating-point numerical accuracy. Results show that the GroqChip achieves the best performance for small networks, yet is unable to simulate large-scale networks. At the scale of mammalian brains, the GPU, IPU and TPU achieve speedups ranging from 29x to 1,208x times over CPU runtimes. Remarkably, the TPU sets a new record for the largest, real-time simulation of the inferior-olivary nucleus in the brain. Reduced-accuracy floating-point implementations make some simulation results unreliable for brain research, notably for the GroqChip. Consequently, this work underscores the potential of ML libraries for accelerating brain simulations as well as the critical role of AI-chip numerical accuracy for biophysically realistic brain models.

Deep random forest with ferroelectric analog content addressable memory.

Deep random forest (DRF), which combines deep learning and random forest, exhibits comparable accuracy, interpretability, low memory and computational overhead to deep neural networks (DNNs) in edge intelligence tasks. However, efficient DRF accelerator is lagging behind its DNN counterparts. The key to DRF acceleration lies in realizing the branch-split operation at decision nodes. In this work, we propose implementing DRF through associative searches realized with ferroelectric analog content addressable memory (ACAM). Utilizing only two ferroelectric field effect transistors (FeFETs), the ultra-compact ACAM cell performs energy-efficient branch-split operations by storing decision boundaries as analog polarization states in FeFETs. The DRF accelerator architecture and its model mapping to ACAM arrays are presented. The functionality, characteristics, and scalability of the FeFET ACAM DRF and its robustness against FeFET device non-idealities are validated in experiments and simulations. Evaluations show that the FeFET ACAM DRF accelerator achieves ∼106×/10× and ∼106×/2.5× improvements in energy and latency, respectively, compared to other DRF hardware implementations on state-of-the-art CPU/ReRAM.

An efficient meshless technique based on collocation and RBFs for solving nonlinear VIEs of third kind with proportional delays

This study provides a numerical scheme for solving nonlinear third-kind Volterra delay integral equations (VDIEs) using mesh-free approaches based on the collocation technique with radial basis functions (RBFs). The proposed approach is stable and requires less computer memory. It combines RBFs and a collocation method technique based on scattered points to represent the solution of third-kind VDIEs by interpolating RBFs using Legendre-Gauss–Lobatto nodes and weights. A description of the approach to the suggested equations is presented. Furthermore, the error analysis of the proposed scheme is investigated. A numerical example that clearly illustrates the validity of the proposed scheme is presented. This problem was also compared with the moving least squares collocation technique and other methods, demonstrating the reliability and efficiency of this approach for solving third-kind VDIEs.

Fast connectivity gradient approximation: maintaining spatially fine-grained connectivity gradients while reducing computational costs

Brain connectome analysis suffers from the high dimensionality of connectivity data, often forcing a reduced representation of the brain at a lower spatial resolution or parcellation. This is particularly true for graph-based representations, which are increasingly used to characterize connectivity gradients, capturing patterns of systematic spatial variation in the functional connectivity structure. However, maintaining a high spatial resolution is crucial for enabling fine-grained topographical analysis and preserving subtle individual differences that might otherwise be lost. Here we introduce a computationally efficient approach to establish spatially fine-grained connectivity gradients. At its core, it leverages a set of landmarks to approximate the underlying connectivity structure at the full spatial resolution without requiring a full-scale vertex-by-vertex connectivity matrix. We show that this approach reduces computational time and memory usage while preserving informative individual features and demonstrate its application in improving brain-behavior predictions. Overall, its efficiency can remove computational barriers and enable the widespread application of connectivity gradients to capture spatial signatures of the connectome. Importantly, maintaining a spatially fine-grained resolution facilitates to characterize the spatial transitions inherent in the core concept of gradients of brain organization.

H-SLAM: Hybrid direct–indirect visual SLAM

The recent success of hybrid methods in monocular odometry has led to many attempts to generalize the performance gains to hybrid monocular SLAM. However, most attempts fall short in several respects, with the most prominent issue being the need for two different map representations (local and global maps), with each requiring different, computationally expensive, and often redundant processes to maintain. Moreover, these maps tend to drift with respect to each other, resulting in contradicting pose and scene estimates, and leading to catastrophic failure. In this paper, we propose a novel approach that makes use of descriptor sharing to generate a single inverse depth scene representation. This representation can be used locally, queried globally to perform loop closure, and has the ability to re-activate previously observed map points after redundant points are marginalized from the local map, eliminating the need for separate map maintenance processes. The maps generated by our method exhibit no drift between each other, and can be computed at a fraction of the computational cost and memory footprint required by other monocular SLAM systems. Despite the reduced resource requirements, the proposed approach maintains its robustness and accuracy, delivering performance comparable to state-of-the-art SLAM methods (e.g., LDSO, ORB-SLAM3) on the majority of sequences from well-known datasets like EuRoC, KITTI, and TUM VI. The source code is available at: https://github.com/AUBVRL/fslam_ros_docker.

A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset

This research paper introduces a memory architecture that handles standard memory storage operations and enables in-memory computations, surpassing the capabilities of conventional SRAM bit-cells. The proposed architecture in this work effectively eliminates read-disturb issues and facilitates bit-wise operations like NAND, NOR, and XNOR, all without requiring intricate analog peripheral circuits. The suggested bit-cell architecture offers enhanced throughput compared to existing In-Memory Computing (IMC) bit-cell architectures, making it a more suitable design for IMC applications. Parallelism offers enhanced throughput due to the unique bit-cell architecture, which allows all the bit-wise operations to be achieved simultaneously in a single cycle. The validity of the suggested architecture has been confirmed through Monte-Carlo variation analysis, utilizing UMC 28 nm PDK transistor models to ensure its robustness. Furthermore, architecture is benchmarked using the CIFAR-10 dataset, which entails assessing its performance across various machine learning models via the NeuroSim Simulator. The proposed architecture offers a substantial increase of up to 40 % in throughput (TOPS/W) compared to the existing architectures. Utilizing accurate Monte-Carlo simulations with 1000 samples, the stability of the proposed 10T bit-cell is validated at worst-case PVT corners, up to 6σ variations.

Multiscale pore‐network reconstruction of a fine‐textured heterogeneous soil

AbstractDigital samples offer many opportunities to study subsurface fluid flow and contaminant transport processes. The pore size distribution of especially fine‐textured porous media often covers many orders of magnitude in the length scale, which makes accurate microCT scanning and modeling of the underlying processes difficult. When a single‐resolution image is not capable of capturing all relevant details of a sample, one should scan the sample, or selected parts of it, at different resolutions. Combining multiple resolutions into one single sample for subsequent pore‐scale modeling is generally not possible due to limitations in computer memory and speed, thus making it necessary to create a simpler sample containing relevant information from the parent networks. We imaged four samples using different resolutions to capture the multiscale heterogeneity of a fine‐textured soil and combined them into one overall digital sample based on the original pore networks. The parent networks were characterized using their geometrical properties, correlations between these properties, and connectivity functions describing the network topologies. Our approach creates stochastic networks of arbitrary size with the same flow properties as the parent network. The method, implemented using the PoreStudio pore network model, repeatedly integrates information at two subsequent scales, with the resulting digital sample having the same hydraulic properties as the original samples. The procedure leads to more useful three‐dimensional digital models, facilitating basic analyses of underlying pore size distributions. Porosity calculations were compared with direct measurements, while those for the hydraulic conductivity were compared with estimates based on the particle size distribution and nearby field data.

A Novel CNFET SRAM-Based Compute-In-Memory for BNN Considering Chirality and Nanotubes

As AI models grow in complexity to enhance accuracy, supporting hardware encounters challenges such as heightened power consumption and diminished processing speed due to high throughput demands. Compute-in-memory (CIM) technology emerges as a promising solution. Furthermore, carbon nanotube field-effect transistors (CNFETs) show significant potential in bolstering CIM technology. Despite advancements in silicon semiconductor technology, CNFETs pose as formidable competitors, offering advantages in reliability, performance, and power efficiency. This is particularly pertinent given the ongoing challenges posed by the reduction in silicon feature size. We proposed an ultra-low-power architecture leveraging CNFETs for Binary Neural Networks (BNNs), featuring an advanced state-of-the-art 8T SRAM bit cell and CNFET model to optimize performance in intricate AI computations. Through meticulous optimization, we fine-tune the CNFET model by adjusting tube counts and chiral vectors, as well as optimizing transistor ratios for SRAM transistors and nanotube diameters. SPICE simulation in 32 nm CNFET technology facilitates the determination of optimal transistor ratios and chiral vectors across various nanotube diameters under a 0.9 V supply voltage. Comparative analysis with conventional FinFET-based CIM structures underscores the superior performance of our CNFET SRAM-based CIM design, boasting a 99% reduction in power consumption and a 91.2% decrease in delay compared to state-of-the-art designs.

Molybdenum Disulfide Memristors for Next Generation Memory and Neuromorphic Computing: Progress and Prospects

AbstractIn the last 15 years memristors have been investigated as devices for high‐density, low‐power, non‐volatile, resistive random access memory (ReRAM) beyond Moore's law. They also show potential in neuromorphic logic architectures to overcome the Von–Neumann bottleneck of classical circuitry facilitating better hardware for artificial intelligence (AI) and artificial neural network (ANN) systems. Molybdenum disulfide (MoS2) has emerged as a promising material for memristor devices of monolayer thickness due to its direct bandgap, high carrier mobility and environmental stability. In this review, recent progress in the development of MoS2 memristors the current understanding of the mechanisms behind their function are examined. The remaining obstacles to a commercially viable device principle and how these may be surmounted in light of the rapid progress that has already been made are also discussed.

Exploring tungsten-oxygen vacancy synergy: Impact on leakage characteristics in Hf0.5Zr0.5O2 ferroelectric thin films

The recent discovery of ferroelectric properties in HfO2 has sparked significant interest in the fields of nonvolatile memory and neuromorphic computing. Yet, as device scaling approaches sub-nanometer dimensions, leakage currents present a formidable challenge. While tungsten (W) electrodes are favored over traditional TiN electrodes for their superior strain and interface engineering capabilities, they are significantly hampered by leakage issues. In this study, we elucidate a positive feedback mechanism attributable to W electrodes that exacerbates oxygen vacancy defects, as evidenced by density functional theory computations. Specifically, intrinsic oxygen vacancies facilitate the diffusion of W, which, in turn, lowers the formation energy of additional oxygen vacancies. This cascade effect introduces extra defect energy levels, thereby compromising the leakage characteristics of the device. We introduce a pre-annealing method to impede W diffusion, diminishing oxygen vacancy concentration by 5%. This reduction significantly curtails leakage currents by an order of magnitude. Our findings provide a foundational understanding for developing effective leakage suppression strategies in ferroelectric devices.

A 92 fps and 2.56 mJ/Frame Computing-In-Memory-Based Human Pose Estimation Accelerator With Resource-Efficient Macro for Mobile Devices

Human pose estimation (HPE) is a promising solution for accurately understanding the state and context of human actions in virtual reality (VR). A high frame rate with low-power HPE processing is required for a realistic user interaction experience in battery-limited mobile devices. The proposed HPE accelerator is a computing-in-memory (CIM) based accelerator that computes depth-wise separable convolution (DWSC) of a lightweight HPE network. Three key features contribute to a resource-efficient CIM accelerator: 1) Dual-mode CIM computes DWSC with a reconfigurable homogenous architecture, resulting in 2.68 times higher throughput than previous analog CIMs. 2) Effective layeraware unrolling performs bit-parallel computation on dualmode CIM with fewer ADC operations, achieving 46 times higher throughput than before. 3) Adaptive fused inter-macro balancing improves latency balance in layer fusion execution, leading to a 57.0 % higher frame rate than before. The proposed HPE accelerator is implemented in 28nm CMOS technology. It achieves higher computation resource utilization and operates HPE with a low energy-delay product of 27.6 uJ7s in mobile VR devices.

Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network

Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network

Efficiency-Accuracy Trade-Off in Light Field Estimation with Cost Volume Construction and Aggregation.

The Rich spatial and angular information in light field images enables accurate depth estimation, which is a crucial aspect of environmental perception. However, the abundance of light field information also leads to high computational costs and memory pressure. Typically, selectively pruning some light field information can significantly improve computational efficiency but at the expense of reduced depth estimation accuracy in the pruned model, especially in low-texture regions and occluded areas where angular diversity is reduced. In this study, we propose a lightweight disparity estimation model that balances speed and accuracy and enhances depth estimation accuracy in textureless regions. We combined cost matching methods based on absolute difference and correlation to construct cost volumes, improving both accuracy and robustness. Additionally, we developed a multi-scale disparity cost fusion architecture, employing 3D convolutions and a UNet-like structure to handle matching costs at different depth scales. This method effectively integrates information across scales, utilizing the UNet structure for efficient fusion and completion of cost volumes, thus yielding more precise depth maps. Extensive testing shows that our method achieves computational efficiency on par with the most efficient existing methods, yet with double the accuracy. Moreover, our approach achieves comparable accuracy to the current highest-accuracy methods but with an order of magnitude improvement in computational performance.

Efficient in Vivo Neural Signal Compression Using an Autoencoder-Based Neural Network.

Conventional in vivo neural signal processing involves extracting spiking activity within the recorded signals from an ensemble of neurons and transmitting only spike counts over an adequate interval. However, for brain-computer interface (BCI) applications utilizing continuous local field potentials (LFPs) for cognitive decoding, the volume of neural data to be transmitted to a computer imposes relatively high data rate requirements. This is particularly true for BCIs employing high-density intracortical recordings with hundreds or thousands of electrodes. This article introduces the first autoencoder-based compression digital circuit for the efficient transmission of LFP neural signals. Various algorithmic and architectural-level optimizations are implemented to significantly reduce the computational complexity and memory requirements of the designed in vivo compression circuit. This circuit employs an autoencoder-based neural network, providing a robust signal reconstruction. The application-specific integrated circuit (ASIC) of the in vivo compression logic occupies the smallest silicon area and consumes the lowest power among the reported state-of-the-art compression ASICs. Additionally, it offers a higher compression rate and a superior signal-to-noise and distortion ratio.

Distributed Shortest Distance Labeling on Large-Scale Graphs

Distance labeling approaches are widely adopted to speed up the shortest-distance query performance. Due to the explosive growth of data graphs, a single machine can hardly satisfy the requirements of both computational power and memory capacity, which causes an urgent need for efficient distributed methods. As the graph is distributed across different machines, it is inevitable to frequently exchange messages among different machines when deploying the existing centralized distance labeling methods on the distributed environment, thereby producing serious communication costs and weakening the scalability. To alleviate this problem, we design a distributed hop-based index DH-Index , which is designed based on a newly proposed boundary graph structure and restricts the index-based hop number of each connected vertex pair within 4 hops. In addition, we propose a hierarchical algorithm to accelerate the index construction and reduce the communication cost. Furthermore, a bidirectional searching strategy is proposed to efficiently resolve the query tasks based on DH-Index. The comprehensive experimental results on eight real-world graphs demonstrate that DH-Index achieves up to 65.5× and 3 orders of magnitude speedup than the existing methods in indexing time and query performance respectively, and exhibits superior capabilities on memory space, communication cost, and scalability.

An End-to-End In-Memory Computing System Based on a 40-nm eFlash-Based IMC SoC: Circuits, Toolchains, and Systems Co-Design Framework

An End-to-End In-Memory Computing System Based on a 40-nm eFlash-Based IMC SoC: Circuits, Toolchains, and Systems Co-Design Framework

Dynamic Key Generation Using GWO for IoT System

One well-known technological advancement that significantly impacts many things is the Internet of Things (IoT). These include connectivity, work, healthcare, and the economy. IoT can improve life in many situations, including classrooms and smart cities, through work automation, increased output, and decreased worry. However, cyberattacks and other risks significantly impact intelligent Internet of Things applications. Key generation is essential in information security and the various applications that use a distributed system, networks, or Internet of Things (IoT) systems. Several algorithms have been developed to protect IoT applications from malicious attacks; since IoT devices usually have small memory resources and limited computing and power resources, traditional key generation methods are inappropriate because they require high computational power and memory usage. This paper proposes a method of Dynamic Key Generation Method (DKGM) to overcome the difficulty using a specific chaotic map called the Zaslavskii Map and a swarm intelligent algorithm for optimization called Grey Wolf Optimizer (GWO). DKGM's ability to generate several groups-seed numbers using the Zaslavskii map depends on various initial parameters. GWO selects strong generated numbers depending on the randomness test as a fitness function. Three wolfs GWα, GWβ, and GWΩ, are used to simulate the behavior of a pack of grey wolves when attacking prey. The speed and position of each wolf are updated depending on the best three wolves. Finally, use the sets GWα in the round, GWβ in the subkey, and GWΩ in shifting operations of the Chacha20 hash function. The dynamic procedure was used to improve the high-security analysis of the DKGM approach over earlier methods. Simulations show that the suggested method is preferable for IoT applications.