An orbital-optimization algorithm is devised for finding stationary points of seniority-zero wavefunctions applied to quantum-chemical Hamiltonians of full seniority. The algorithm is agnostic to peculiarities of the seniority-zero method, requiring only the availability of its one- and two-electron reduced density matrices. Their simpler structure is exploited to avoid the computationally demanding four-index two-electron integral transformation; instead, intermediary rank-three tensors are constructed, which greatly reduce the consumption of computational resources. In combination with the spatial locality of atomic and molecular orbitals, as well as the sparsity of the seniority-zero density cumulant, the algorithm achieves sub-cubic scaling with system size. A direct inversion in the iterative subspace scheme is applied to accelerate orbital-optimization convergence. Using pECCD as the seniority-zero wavefunction, it is demonstrated that the algorithm succeeds in optimizing large linear oligomer chains and hydrogen 2D/3D clusters with up to 1391 orbitals on modest computer hardware. The method is subsequently applied to predict molecular properties of ozone, the rotational barrier in ethylene, and isomerization energies of organic reactions, where it is benchmarked against conventional quantum-chemical methods.

Spin transfer torques (STTs) control magnetization by electric currents, enabling a range of nano-scale spintronic applications. They can destabilize the equilibrium magnetization state by counteracting magnetic relaxation. Here we maximize the STT effect through a dedicated growth-annealing protocol for CoFeB thin films, such that magnetic anisotropies originating from the interface and shape almost cancel each other. The nearly isotropic magnets enable low-current dynamical stabilization of the magnetization in the direction opposite to an applied magnetic field, thereby realizing a spintronic analogue of the Kapitza pendulum. In an intermediate current regime, the STT drives large magnetization vector fluctuations that cover the entire Bloch sphere. The continuous variable associated with the stochastic magnetization direction may serve as a resource for probabilistic computing and neuromorphic hardware. Our results establish isotropic magnets as a platform to study as-yet-uncharted, far-from-equilibrium spin dynamics including anti-magnonics, with promising implications for unconventional computing paradigms.

The rapid growth of artificial intelligence (AI) is increasingly constrained by fundamental hardware bottlenecks in computation throughput and energy efficiency. Bioinspired computing (BIC) offers a promising alternative by emulating the intrinsic advantages of biological systems, such as parallelism, adaptability, and robustness. Progress in BIC hardware demands interdisciplinary convergence that bridges materials science and device physics with neuroscience, computer science, mathematics, and information science. Therefore, the development of this cross-disciplinary field urgently requires a comprehensive roadmap that analyzes systematically and in-depth the frontier issues and the latest progress. In this roadmap, we categorize the critical challenges into three components: hardware foundations, architectures, and prototype realizations. We highlight how biological features inspire the design of BIC hardware through device physics and discuss their performance metrics and engineering challenges. We then describe how diverse signaling rules and structural organizations in BIC architectures support specific computational prototypes, including electronic and photonic BIC chips, and present a technological roadmap that outlines opportunities to expand the functional scope of BIC hardware through coordinated advances in devices, architectures, and system demonstrations. This ongoing convergence of interdisciplinary knowledge can help accelerate the shift toward high-efficiency AI hardware.

Autonomous materials science, where active learning is used to navigate large compositional phase space, has emerged as a powerful vehicle to rapidly explore new materials. A crucial aspect of autonomous materials science is exploring new materials using as little data as possible. Gaussian process-based active learning allows effective charting of multi-dimensional parameter space with a limited number of training data and, thus, is a common algorithmic choice for autonomous materials science. An integral part of the autonomous workflow is the application of kernel functions for quantifying similarities among measured data points. A recent theoretical breakthrough has shown that quantum kernel models can achieve similar performance with less training data than classical kernel models. This signals the possible advantage of applying quantum kernel machine learning to autonomous materials discovery. In this work, we compare quantum and classical kernels for their utility in sequential phase space navigation for autonomous materials science. In particular, we compute a quantum kernel and several classical kernels for x-ray diffraction patterns taken from an Fe–Ga–Pd ternary composition spread library. We conduct our study on both IonQ’s Aria trapped ion quantum computer hardware and the corresponding classical noisy simulator. We experimentally verify that a quantum kernel model can outperform some classical kernel models. The results highlight the potential of quantum kernel machine learning methods for accelerating materials discovery and suggest that complex x-ray diffraction data are a candidate for robust quantum kernel model advantage.

The exponential scaling of Large Language Models (LLMs) has exposed a growing mismatch between computational demands and hardware efficiency. Although model compression is essential for mitigating this gap, two bottlenecks fundamentally limit its effectiveness in practice: (1) high-magnitude activation outliers that degrade the accuracy of conventional uniform quantization, and (2) dynamically varying activation sparsity that is difficult to exploit with rigid hardware datapaths. Existing index-based schemes, such as mixed-precision or non-uniform quantization, often incur prohibitive energy and area overheads due to the complex decoding logic required at runtime. In this paper, we propose NICE, an index-assisted algorithm-hardware co-design framework that achieves high-efficiency DNN acceleration by synergistically exploiting unstructured weight sparsity and centroid-based activation indexing. The core philosophy of NICE is to reformulate computation-intensive Multiply-Accumulate (MAC) operations into a unified table-lookup (LUT) mechanism. Specifically, we design a new hardware primitive that treats static weight sparsity and dynamic activation indices as lookup coordinates, enabling the direct retrieval of pre-computed or quantized results. Building on this, we develop the NICE Architecture, a systolic array-based accelerator that introduces novel dimensions of data-and-index reuse, effectively alleviating the data-movement bottlenecks of traditional architectures. Experiments show that NICE can achieve 51.3% energy reduction and 3.83x speedup on average.

Major crops worldwide are affected by various diseases yearly, leading to crop losses in different regions. The primary methods for addressing crop disease losses include manual inspection and chemical control. However, traditional manual inspection methods are time-consuming, labor-intensive, and require specialized knowledge. The preemptive use of chemicals also poses a risk of soil pollution, which may cause irreversible damage. With the advancement of computer hardware, photographic technology, and artificial intelligence, crop disease recognition methods based on spectral and red-green-blue (RGB) images not only recognize diseases without damaging the crops but also offer high accuracy and speed of recognition, essentially solving the problems associated with manual inspection and chemical control. This paper summarizes the research on disease recognition methods based on spectral and RGB images, with the literature spanning from 2020 through early 2025. Unlike previous surveys, this paper reviews recent advances involving emerging paradigms such as State Space Models (e.g., Mamba) and Generative AI in the context of crop disease recognition. In addition, it introduces public datasets and commonly used evaluation metrics for crop disease identification. Finally, the paper discusses potential issues and solutions encountered during research, including the use of diffusion models for data augmentation. Hopefully, this survey will help readers understand the current methods and effectiveness of crop disease detection, inspiring the development of more effective methods to assist farmers in identifying crop diseases.

Coarse-grained reconfigurable architecture (CGRA) has increasingly begun to be used across a wide range of edge computing due to its characteristics, such as high performance, low power consumption and versatility. Versatility is usually considered an important design principle of traditional CGRA architectures during architectural design. On the other hand, the traditional CGRA architecture must take into account the execution of control flow-intensive programs. LUNA, an AI chip with features of separate memory access, computation and reconfigurable hardware connections toward edge neural network computing, can handle vector, matrix, and convolution operations uniformly, which poses great challenges to the generation of configuration information. This paper aims to research the configuration information compilation and generation methods for the new CGRA architecture, and design a counter array allocation strategy based on loop analysis to solve the configuration information generation problem of memory access addresses. Additionally, this paper proposes a hardware connection generation method to address the configuration information generation problem of reconfigurable hardware connections. The hardware configuration information generation method presented in this paper, which is proven to be effective through testing with vector, matrix and other datasets, is said to achieve a performance of over 95% as compared to hand-optimized assembly.

Abstract Low-temperature plasmas (LTPs) are essential to both fundamental scientific research and critical industrial applications. As in many areas of science, numerical simulations have become a vital tool for uncovering new physical phenomena and guiding technological development. Code benchmarking remains crucial for verifying implementations and evaluating performance. This work continues the Landmark benchmark initiative, a series specifically designed to support the verification of LTP codes. In this study, seventeen simulation codes from a collaborative community of nineteen international institutions modeled a partially magnetized E × B Penning discharge. The emergence of large scale coherent structures, or rotating plasma spokes, endows this configuration with an enormous range of time scales, making it particularly challenging to simulate. The codes showed excellent agreement on the rotation frequency of the spoke as well as key plasma properties, including time-averaged ion density, plasma potential, and electron temperature profiles. Achieving this level of agreement came with challenges, and we share lessons learned on how to conduct future benchmarking campaigns. Comparing code implementations, computational hardware, and simulation runtimes also revealed interesting trends, which are summarized with the aim of guiding future plasma simulation software development.

The conventional computer architecture has been facing challenges answering the ever-increasing demands from emerging applications, such as AI, for energy-efficient computation and memory hardware systems. Computational Random Access Memory (CRAM) represents a true in-memory computing paradigm that integrates logic and memory functions within the same array. At its core, CRAM relies on Magnetic Tunnel Junctions (MTJs), which serve as the foundational building blocks for implementing both memory storage and logic operations. However, a key challenge in CRAM lies in the non-ideal error rates associated with switching dynamics of MTJs, necessitating innovative approaches to reduce errors and optimize logic margins. This work proposes a novel approach of utilizing the voltage-controlled magnetic anisotropy (VCMA) to steepen the switching probability transfer curve (SPTC), thereby significantly reducing the logic operation error rate in CRAM. Using several numerical modeling tools, we validate the effectiveness of VCMA in modulating the energy barrier and switching dynamics in MTJs. It is revealed that the VCMA effect significantly reduces the error rate of CRAM by 61.43% at a VCMA coefficient of 200 fJ·V−1m-1 compared to CRAM without VCMA. The reduction of error rate is further rapidly amplified with an increasing TMR ratio. Furthermore, the introduction of the VCMA effect decreases the logic voltage (Vlogic) required for logic operations in CRAM and results in reduction of energy consumption. Our work serves as a first exploration in reducing the error rate in CRAM by modifying SPTC in MTJs.

The expansion of Internet of Things (IoT) ecosystems and cyber–physical systems has shifted artificial intelligence processing from centralized cloud infrastructures to resource-constrained edge devices. Although edge computing enables lower latency, reduced network congestion, and enhanced data privacy, it also presents significant obstacles for deep learning training due to limited computation power, energy constraints, and hardware heterogeneity. To address these challenges, this paper introduces a Hybrid Parallel Distributed Deep Learning Framework tailored for heterogeneous edge environments. The proposed approach integrates data parallelism and model parallelism to efficiently utilize diverse edge resources. Workload distribution is adaptively managed based on device capabilities, network variability, and energy availability. Experimental evaluations using image classification tasks show that the proposed framework achieves superior training efficiency, improved energy utilization, and enhanced model performance when compared with centralized cloud training and single-parallel edge learning methods.

ABSTRACT Perovskite memristors are redefining the landscape of memory storage and neuromorphic computing by combining rich ion dynamics, ultralow voltage switching, cost‐effective solution processability, and excellent scalability within a single material platform. Harnessing their intrinsic stochasticity in conductive filamentary switching provides a physical route to true random number generation and a unique window into the fundamental physics of resistive switching. Herein, we investigate solution‐processed ITO/Cs 0.1 FA 0.9 PbI 3 /Ag organic–inorganic hybrid halide perovskite (OIHP) memristors that exhibit low voltage switching (∼0.29 V) with distinct cumulative function (∼100x) between ON/OFF states, demonstrating stability of 10 3 cycles and providing a clear mechanism of OIHP‐based memristors, thereby advancing fundamentals of next‐generation neuromorphic computing and practical hurdles in electronics hardware. Investigating the elemental analysis at the buried interface via X‐ray photoelectron spectroscopy (XPS) and energy dispersive X‐ray spectroscopy (EDX) reveal previously overlooked and underexplored phenomena at the ITO‐perovskite junction, offering essential understanding into the switching mechanism. Additionally, pulse stress testing with sharp 500 µs‐wide excitation demonstrates robust endurance and concurrently exposing the intrinsic complexity and dynamic unpredictability of filamentary interactions. These results unveil the mechanistic understanding of FA‐based OIHP memristors and also provide vital insights into their potential in large‐scale, brain‐inspired architectures for neuromorphic computing and secure information processing.

This paper describes the design and development of an E-commerce Hardware Website that enables customers to purchase computer hardware components through an online platform. The proposed system is designed to simplify the hardware buying process by providing structured product listings, specification- based selection, secure payment processing, and automated order management. The platform integrates essential web technologies to support user registration, product browsing, shopping cart operations, order confirmation, and inventory updates. A key focus of the system is to provide a reliable and user-friendly interface that supports both individual customers and administrators. The website also supports real-time pricing visibility and system customization features to assist users in making informed purchasing decisions. Experimental evaluation of the system shows improved accessibility, reduced manual processing, and faster transaction completion when compared to traditional offline hardware stores. The results confirm that web-based e-commerce solutions can significantly enhance efficiency and customer experience in the hardware retail domain.

Instantaneous Noise-Based Logic (INBL) presents a classical noise-based computing framework as an alternative to quantum computation, though some logic gates remain unimplemented for achieving universality over superpositions. INBL encodes M noise-bits using 2M orthogonal stochastic reference noises to construct a 2 M -dimensional product-based Hilbert space (hyperspace). Vectors in this hyperspace correspond to products of reference noises representing bit values in M-bit binary strings. This work introduces INBL implementations of XOR and XNOR operations targeting specific bits, facilitating pairwise operations directly between strings of equal length or hyperspace vectors, which are the longest strings. These operations naturally extend to superpositions, potentially delivering significant improvements in computational speed and hardware complexity. Diverging from previous methods by Khreishah et al., our approach avoids direct manipulation of the reference noise system, enabling more flexible and general-purpose implementations. We validate INBL operations—including NOT, XOR, and XNOR—through simulation using random telegraph waves, demonstrating practical feasibility without explicit reference noise manipulation.

in the 21st century emerging digital era, keeping computers running smoothly is crucial. Since, maintenance of computers is imperative for efficient operations. This paper developed an intelligent expert system for Hardware-Software Repair Using Artificial Intelligence (AI). The study tries to revolutionize computer maintenance in mitigating the consistent struggle with tech issues that need specialized knowledge, the AI based application system is designed to accept input and generate solutions to the problems accordingly. The research developed and implemented an Intelligent Expert System for computer hardware and software repairs also known as an Intelligent Tech-Stack Repair Expert System using AI. The study employed Natural Language Processing (NLP) techniques to interpret user queries and synonym handling for enhanced query matching. Pre-trained models as BERT and cosine similarity were applied for accurate troubleshooting. Additionally, the system focuses on scalability, a refined user interface, and machine learning (ML) integration was used to enhance its knowledge base and performance. The results significantly improved efficiency in diagnosing and recommending Computer repairs for hardware-software devices.

Like other computer hardware components, the central processing unit (CPU) generates heat during operation and requires effective cooling to maintain optimal performance. One of the most efficient methods for cooling a CPU is the use of a liquid-based cooling system. This system typically consists of three main components: a fluid block that makes direct contact with the CPU, a pump, and a heat exchanger, which includes a fan and a radiator. The coolant circulates through the system via connecting pipes. In this study, the thermal and hydraulic performance of a CPU cooler was analyzed under various operating conditions. Water was used as the working fluid (coolant) in the system. A 100 W thermoelectric heater was employed to simulate the thermal load and to determine the cooling capacity of the system. The volumetric flow rates of the coolant were set to 1, 2, 3, and 4 L/min, respectively. It was observed that the heat transfer between the CPU surface and the cooler decreased with increasing fluid velocity. The fluid pressure was higher at the inlet of the cooler and decreased along the flow path, depending on both the geometry of the flow channels and the flow rate of the coolant. For effective heat dissipation in CPU cooling systems, it is crucial to maintain the coolant flow rate and velocity within an optimal range.

The computational demands of next-generation (Next-Gen) communication systems pose major challenges for real-time signal processing, particularly in digital predistortion (DPD), which is essential for linearizing power amplifier (PA) nonlinearities. While traditional DPD methods-such as polynomial and Volterra series models-remain prevalent, neural network (NN)-based approaches offer superior modeling accuracy and adaptability. However, their deployment is hindered by high computational complexity, limited scalability, and hardware integration challenges. This review presents a comprehensive analysis of NN-based DPD techniques and hardware acceleration strategies for efficient real-time implementation. We assess the strengths of various NN architectures-deep, convolutional, recurrent, and hybrid-and evaluate their tradeoffs across graphics processing unit (GPU), field-programmable gate arrays (FPGA), and application-specific integrated circuits (ASIC) platforms. We also examine key challenges, including fragmented evaluation standards and limited real-world validation. Finally, we outline future directions emphasizing model-hardware codesign, reconfigurable computing, and on-chip learning to enable scalable, energy-efficient DPD for 5G, 6G, and beyond.

Abstract Seismic imaging has undergone transformative advances over the past four decades, driven by the coevolution of migration algorithms and high-performance computing (HPC) architectures. ExxonMobil’s journey, from Kirchhoff prestack depth migration to elastic full-waveform inversion, exemplifies how innovations in algorithmic complexity have been enabled by progressive leaps in compute density, memory bandwidth, and energy efficiency. This article traces the history of seismic imaging, inversion, and compute infrastructure at ExxonMobil, highlighting key milestones in algorithm development, hardware acquisition, and workflow integration. It further explores the emerging challenges and opportunities presented by 4D seismic monitoring, hybrid physics-AI workflows, and future HPC architectures. The narrative underscores that sustained advances in subsurface imaging depend on a holistic approach combining physics-based modeling, scalable computing, and power-efficient hardware, poised to unlock unprecedented subsurface insights.

This study investigates the integration of Ancient Indian Vedic Mathematics (AIVM) into contemporary cryptographic frameworks, with a particular emphasis on Elliptic Curve Cryptography (ECC). Cryptographic computations in ECC require substantial computational resources and execution time, especially during core operations such as point addition, point doubling, and modular multiplication. The AIVM system, based on sixteen Sutras and fourteen Sub-sutras, offers efficient and high-speed arithmetic techniques. This paper examines the applicability and performance benefits of the Urdhva-Tiryagbhyam sutra for multiplication, the Dvandva-Yoga sutra for squaring operations, and the Nikhilam Navatashcaramam Dashatah sutra for handling large-number computations. By implementing these ancient techniques, the computational latency and hardware complexity of systems like RSA and ECC can be significantly reduced. The survey demonstrates that Vedic algorithms not only accelerate encryption and decryption processes but also optimize hardware resource utilization, making them highly suitable for high-speed security applications. Keywords: ECC, Vedic Mathematics, Dhvajanka, Cryptography, Dvandva-Yoga, Urdhva-Tiryagbhyam, Nikhilam Navatashcaramam Dashatah.

Creating an environment conducive to learning for today's growing young generation remains a challenge. The current educational landscape is in a crucial phase, needing to transform the future world into a knowledgeable and empowered society. The use of computers plays a vital role in Tamil research platforms. Globalization and liberalization policies have paved the way for computers, websites, and the internet to be easily accessible even to rural students. Information technology is not merely a single technology; it is a blend of several technologies such as computer networks, the internet, satellites, hardware, software, and media. This Information and Communication Technology (ICT) simplifies and enriches the teaching and learning environment in many dimensions.

Quantum error correction provides a route to realizing large-scale quantum computation but incurs substantial resource overheads. Here we highlight recent advances that reduce these overheads by co-designing different levels of the computational stack, including algorithms, quantum-error-correction strategies and hardware architecture. We then discuss opportunities for further optimization such as leveraging flexible qubit connectivity and quantum low-density parity check codes. These strategies can bring useful quantum computation closer to reality as experiments advance in the coming years.