Computer Circuit Simulation Research Articles

ENERGY EFFICIENCY OF THE POWER AMPLIFIER ACCORDING TO W. DOHERTY’S SCHEME WITH AUTOMATIC POWER ADJUSTMENT

At present, in relation to the power amplifiers of digital television broadcast transmitters, the scheme proposed by engineer William Dougherty for the construction of broadcast transmitters with amplitude modulation is widely used. W. Dougherty’s method, today is practically the only solution for improving the energy efficiency of OFDM signal power amplifiers, as applied to terrestrial digital television transmitters, when the wide band of the envelope of such a signal does not allow the construction of a transmitter based on a polar architecture. Transmitters for digital terrestrial television broadcasting using linear power amplifiers built on the basis of the W. Doherty method are developed and produced. When building transmitters for terrestrial digital television broadcasting, the problem of ensuring an acceptable efficiency of a linear power amplifier is very acute. The main reason for the low efficiency of such amplifiers is the high OFDM crest factor of the digital television radio signal. The problem of increasing the linear power amplifiers average efficiency of digital broadcasting transmitters is considered. The joint application of two methods for constructing high-efficiency linear power amplifiers is discussed: the method of William Dougherty and method of automatic power mode control. Preliminary assessment results of the energy gain from the combined use of these two methods, obtained by computer circuit simulation, are presented.

RESEARCH DEPENDENCE TOTAL HARMONIC DISTORTION FROM FREQUENCY IN AMPLIFIERS WITH DIFFERENT TYPES AND DEPTHS OF NEGATIVE FEEDBACK

In work examined one of the methods obtaining the dependence of the harmonic distortion from frequency in audio power amplifier for computer circuit simulation was investigated. This made it possible to assess for the first time the influence of both the form and the depth of the negative feedback on the dependence total harmonic distortion from frequency and to reveal the conditions under which an increase in the depth of the negative feedback leads to an increase in the harmonic coefficient. The study does not show the effect of each individual cascade on the dependence of the harmonic coefficient on frequency. The study was carried out at voltage gain (GV) equal to 60, 50, 40, 30 and 20 decibels, where GV =60dB corresponds to the minimum negative feedback (NF) depth, and GV =20dB to the maximum NF depth. To obtain the dependence total harmonic distortion (THD) factor THD=F(f) in the MicroCap11 simulation program, Harmonic Distortion analysis was used.

Handwritten Numeric Image Classification with Quantum Neural Network using Quantum Computer Circuit Simulator

Quantum Computer is a computer machine using principles of quantum mechanics in doing its computation. The Quantum Computer Machine itself is still in the development stage and has not been deployed yet, however TensorFlow provides a library for hybrid quantum-classical machine learning called TensorFlow Quantum (TFQ). One of the quantum computing models is the Quantum Neural Network (QNN). QNN is adapted from classical neural networks capable of processing qubit data and passing quantum circuits. QNN is a machine learning model that allows quantum computers to classify image data. The image data used is classical data, but classical data cannot reach a superposition state. So in order to carry out this protocol, the data must be readable into a quantum device that provides superposition. QNN uses a supervised learning method to predict image data. Quantum Neural Network (QNN) with a supervised learning method for classifying handwritten numeric image data is implemented using a quantum computer circuit simulation using the Python 3.6 programming language. The quantum computer circuit simulation is designed using library Cirq and TFQ. The classification process is carried out on Google Colab. The results of training on the QNN model obtained a value of 0.337 for the loss value and 0.3427 for the validation loss value. Meanwhile, the hinge accuracy value from the training results is 0.8603 for the hinge accuracy value with training data and 0.8669 for the hinge accuracy validation value. Model testing is done by providing 100 handwritten number images that are tested, with 53 image data of number three and 47 image data of number six. The results obtained for the percentage of testing accuracy are 100% for the number three image and 100% for the number six image. Thus, the total percentage of testing is 100%.

Исследование влияния шумов на работу зарядочувствительного усилителя с компенсацией пироэлектрической помехи

The authors consider the problems that arise during the operation of the charge sensitive amplifier (CSA) in critical conditions. Simplified schemes and mathematical models of the CSA are presented in order to study the effect of noise of operational amplifier and high-resistance resistor of negative feedback loop. The dependence of the CSA noise level on the pyroelectric interference compensation value is studied. Mathematical analysis data is confirmed by computer circuit simulation.

USING CIRCUIT SIMULATION TOOLS WITH TAGUCHI DESIGN OF EXPERIMENT TECHNIQUES TO OPTIMIZE THE PERFORMANCE OF A DIGITAL HALF-ADDER INTEGRATED CIRCUIT

This article describes a method by which a subcircuit of a semiconductor device was successfully optimized using a Taguchi-designed experiment in conjunction with computer circuit simulation tools. The delay time of a digital half-adder, which is a subc..

Enhanced peaking current reference

Enhancements of the peaking current reference with significantly improved supply voltage and temperature independence are discussed. The addition of current mirror circuitry forces the peaking source to operate near its optimum operating range at all times; the optimum bias conditions for this source differ from those of a previously presented (K. Fukahari et al. 1979) basic peaking source. A theory for optimization is developed and practical application of this source, computer circuit simulations and experimental data are presented. >

Parameter tolerance design for electrical circuits

AbstractRealistic circuit design requires that unavoidable tolerances on component parameters be taken into account, particularly in situations where a circuit is to be mass‐produced. Since specifications are normally imposed on circuit performance, parameter tolerances can have the undesirable effect of reducing manufacturing yield (i.e. the percentage of circuits which meet specifications) to values below unity, thereby effectively increasing circuit cost.Approaches have been developed to electrical circuit design which incorporate aspects of parameter tolerance variations at the various stages of design, thus enabling tolerance effects to be assessed and minimized. There are two principal approaches: statistical and deterministic. The first uses probabilistic techniques to predict variations in circuit performance, whereas the second uses deterministic (i.e. non‐stochastic) methods. Within each group, three types of problems are important: first, the maximization of yield, secondly, the minimization of circuit unit cost and, thirdly, the minimization of performance variability. This paper discusses some important advances in the statistical approach to tolerance design. Monte Carlo analysis is almost invariably an important component of the procedure: random fluctuations in parameter values are simulated according to some probability density function and inserted into a computer circuit simulation program which computes corresponding circuit performance variations. The procedure — also referred to as tolerance analysis — not only allows the designer to predict expected performance fluctuations but also presents him with information regarding the relative location of acceptable and non‐acceptable circuits in component parameter space. The Monte Carlo method can handle without difficult any number of component parameters and performance functions; moreover, statistical dependence among parameters is readily handled.The algorithm presented here is experimentally validated through successful design of practical circuits and is applicable to both discrete and integrated circuits. Strategies which ensure computational efficiency of the methods are discussed and a cost/benefit analysis carried out for a typical circuit.

Single-Event Upset (SEU) Model Verification and Threshold Determination Using Heavy Ions in a Bipolar Static RAM

Single-Event Upset (SEU) response of a bipolar low-power Schottky-diode-clamped TTL static RAM has been observed using Br ions in the 100-240 MeV energy range and 0 ions in the 20-100 MeV range. These data complete the experimental verification of circuit-simulation SEU modeling for this device. The threshold for onset of SEU has been observed by the variation of energy, ion species and angle of incidence. The results obtained from the computer circuit-simulation modeling and experimental model verification demonstrate a viable methodology for modeling SEU in bipolar integrated circuits.

Modeling of avalanche generation current of bipolar junction transistors for computer circuit simulation

An avalanche generation model is developed and implemented in a circuit simulation program SLIC. The model provides accuracy, as well as simplicity in parameter extraction. Computer programs are developed for automated measurement and parameter determination of model coefficients. Comparison of measured and simulated results shows good agreement.

High-speed split-emitter I/sup 2/L/MTL memory cell

Describes a novel circuit/device approach that overcomes the performance drawback of the injection-sensed I/SUP 2/L/MTL memory cell cited in a 16-kbit static MTL RAM (see IEEE ISSCC Dig. Tech. Papers, p.222-4, 1980). As a result, a compact memory cell with extremely low DC standby power in the nanowatt range and with read/write times below 5 ns is achieved. This has been verified by experimental investigations on small test arrays. They have been fabricated with an advanced process featuring a p-polysilicon-base self-alignment scheme and a double-diffused p-n-p structure. In addition, computer circuit simulations have been performed that show the read delay sensitivities in large arrays. Based on these results, an access time of less than 25 ns is projected for a 16-kbit MTL RAM.

A Zener diode model for computer circuit simulations

A Zoner diode equivalent circuit suitable far CAD programmes and containing no sources is developed that models the large-signal V-I Zener curve, temperature coefficient of Zener voltage, and small signal resistance.

The Hybrid Integration of a Multistage Active Bandpass Filter/Amplifier

This paper describes the fabrication, characterization, and analysis of a hybrid microcircuit to be used as a signal amplifier and conditioner for an IR tracking system. The entire circuit is integrated on a 1 X 2-in alumina substrate using thick-film resistors and conductors, some chip resistors in critical locations, chip capacitors, and monolithic integrated-circuit (IC) operational-amplifier (op-amp) chips. Fig. 1 shows a block diagram of the entire circuit. The transfer functions of each of the stages is derived. The predicted gain. peak and the shape of the measured bandpass agree well with experimental results. The computer simulation using an opamp "macromodel" [1] gives results very closely resembling the measured bandpass, and underscores the utility of computer circuit simulations in IC development. Stability and hybrid layout considerations are discussed. The noise figure is measured as a function of frequency for the given system source impedance of 5 M <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\Omega</tex> and also for 0.5 M <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\Omega</tex> to indicate the dependence of the noise figure on source resistance. The dominant sources of noise in the amplitier/filter and low-noise design considerations are discussed.

A two-lump transistor model for computer circuit simulation

Base resistance is calculated using DC measurements of base current as a function of base-emitter voltage. It is shown that a two-transistor lumped model gives an excellent fit to the measured data. The physical basis for model partitioning and the extension of the model to AC applications is discussed.

Bipolar transistor modeling of avalanche generation for computer circuit simulation

An avalanche generation model is developed and incorporated into computer circuit analysis programs SLIC and NICAP. A modified form of Miller's empirical expression for generation is found to agree well with measured data for Western Electric and commercial n-p-n transistors. Measurement techniques and parameter determination for the three model coefficients are discussed. Equation constraints appropriate for computer implementation are presented.

Optimization of the latching pulse for dynamic flip-flop sensors

Analysis of dynamic IGFET flip-flop charge sensors shows that the optimum latching waveform is an initial voltage step followed by a ramp of gradually increasing slope. Latchup time is approximately inversely proportional to the initial voltage imbalance. Capacitive coupling between the two sides of the flip-flop generates a voltage excursion of the off-side even when there is no off-side conduction. With a 10-V latching ramp, the off-side is no off-side conduction. With a 10-V latching ramp, the off-side voltage excursion is typically about 2 V, and full latchup is attained in about 75 ns for an initial imbalance of 0.5 V. If a small off-side conduction is allowed, then latchup time can be reduced by a factor of two or more. The penalty is a few tenths of a volt added excursion of the off-side voltage. Computer circuit simulations were used to verify the analytic derivations.