Computationally-intensive Operations Research Articles

Deep Learning-Based X-Ray Baggage Hazardous Object Detection – An FPGA Implementation

This work proposes deep learning neural network-based X-ray image classification. The X-ray baggage scanning machinery plays an essential role in the safeguard of customs, airports, and other systematically very important landmarks and infrastructures. The technology at present of baggage scanning machines is designed on X-ray attenuation. The detection of threatful objects is built on how different objects attenuate the X-ray beams going through them. In this paper, the deep convolutional neural network of YOLO is utilized in classifying baggage images. Real-time performance of the baggage image classification is an essential one for security scanning. There are many computationally intensive operations in the You Only Look Once (YOLO) architecture. The computational intensive operations are implemented in the Field Programmable Gate Array (FPGA) platform to optimize process delays. The critical issues involved in those implementations include data representation, inner products computation and implementation of activation function and resolving these issues will also be a significant task. The FPGA implementation results show that with less resource occupancy, the YOLO implementation provides maximum accuracy of 98.9% in classifying X-ray baggage images and identifying hazardous materials. This result proves that the proposed implementation is best suited for practical system deployments for real-time Baggage scanning.

Can graph properties determine future grid adequacy for power injection diversity?

Engineers need new tools to design future power grids able to accommodate an increasing diversity of power injection operating states. Graph-based grid expansion tools are an emerging approach that exploits the underlying graph properties of power grids to inform preliminary stages of decision-making. The simplicity of graph-based approaches circumvents the need for computationally-intensive operations modeling, but extensive testing on its effectiveness in capturing and improving actual grid performance is lacking. This work provides experimental results that explore the efficacy of four graph-based grid-expansion approaches in improving grid adequacy. We rank and compare grid expansion options using four graph metrics and three inadequacy metrics to see whether graph metrics are good predictors of grid adequacy. Results for a 6- and a 118-bus test system show that grid designs that are top-ranking in terms of the graph metrics are not necessarily top-ranking in terms of the grid inadequacy metrics, and vice versa. Nonetheless, high-ranking grid designs in terms of some graph metrics can be high-ranking as well in terms of some grid inadequacy metrics – an observation that can be useful in some applications. The case studies illustrate that using the four graph-based grid expansion heuristics explored may not necessarily lead to optimal grid adequacy. How prevalent this observation is to other test systems and actual grids and whether there exist special classes of grids wherein graph-based grid expansion result in optimal grid adequacy will be interesting areas for future work.

Mining Discriminative K-Mers in DNA Sequences Using Sketches and Hardware Acceleration

Extracting discriminative k-mers is an important and challenging problem in DNA sequence analysis with applications in metagenomics and motif discovery. Despite the availability of multiple computational tools designed for this purpose, most discriminative k-mer discovery methods suffer from long execution times and high memory usage when processing large datasets. This paper presents a novel approach for discriminative k-mer discovery in DNA sequences, which leverages streaming and sketch algorithms to reduce space complexity and expose data parallelism, enabling the use of parallel platforms for accelerating the execution of computationally-intensive operations. To assess the performance of our method, we designed and implemented two versions of the algorithm that leverage parallelization at different levels: (i) a software version tailored for multithreading and vector instructions in commodity CPUs, and (ii) a custom architecture implemented on a Field-Programmable Gate Array (FPGA) accelerator that exploits fine-grain parallelism and deep pipelining on reconfigurable logic. Experimental results show that, when mining discriminative k-mers from a set of well-known ChIP-seq sequences, our parallel software implementation executes at least 15% faster than exact-counting tools, and requires at least five times less memory when processing large datasets. More importantly, we designed a custom FPGA-based accelerator for our algorithm on a Xilinx KCU1500 board, which achieves speedups above 78x with the largest datasets, compared to our parallel software implementation. The accelerator uses less than 3% of the logic resources available on the on-board XCKU115 Kintex-7 Ultrascale FPGA, and between 12% and 70% of the memory resources, depending on the size of the dataset.