The extension of Amdahl's law and Gustafson-Barsis' law presented in this article provides insight into the relationship between communication costs and network topology in parallel computing. By considering communication latency in parallel computation execution time, these extensions can help researchers and developers optimize the interconnected network architecture of processing nodes and improve the performance of parallel computing systems. Today, parallel computer systems consisting of hundreds and thousands of processing nodes based on multiprocessor chip technology, high-speed optical transmission such as supercomputers are being researched, developed, and applied in many fields many areas. Although chip technology has progressed to the 3 nm process, the network architecture connecting processing nodes continues to be a problem that greatly affects the communication delay in the parallel computation time of the applications. In this paper, extensions of Amdahl's law and Gustafson-Barsis' law are presented with the addition of communication costs depending on the topology of the topology. These extensions provide insight into the relationship between communication costs and network topology in parallel computing. By considering communication latency in parallel computation execution time, these extensions can help researchers and developers optimize the interconnected network architecture of processing nodes and improve the performance of parallel computing systems.
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