Discrete Cosine Transform Computation Research Articles

A Deterministic Low-Complexity Approximate (Multiplier-Less) Technique for DCT Computation

The approximate (multiplier-less) two-dimensional discrete cosine transform (DCT) is a widely adopted technique for image/video compression. This paper proposes a deterministic low-complexity approximate DCT technique that accurately configures the size of the transform matrix ( ${T}$ ) according to the number of retained coefficients in the zigzag scanning process. This is achieved by establishing the relationship between the number of retained coefficients and the number of rows of the ${T}$ matrix. The proposed technique referred to as the zigzag low-complexity approximate DCT (ZLCADCT), when compared with approximate DCT (ADCT), decreases the number of addition operations and the energy consumption while retaining the PSNR of the compressed image. In addition, the ZLCADCT eliminates the zigzag scanning process used in the ADCT. Moreover, to characterize the deterministic operation of the ZLCADCT, a detailed mathematical model is provided. A hardware platform based on FPGAs is then utilized to experimentally assess and compare the proposed technique; as modular, deterministic, low latency, and scalable, the proposed techniques can be implemented upon any change in the number of retaining coefficients by realizing only a partial reconfiguration of the FPGA resources for the additional required hardware. The extensive simulation and experimental results show the superior performance compared to previous ADCT techniques under different metrics.

Efficient Computation of the 8-point DCT via Summation by Parts

This paper introduces a new fast algorithm for the 8-point discrete cosine transform (DCT) based on the summation-by-parts formula. The proposed method converts the DCT matrix into an alternative transformation matrix that can be decomposed into sparse matrices of low multiplicative complexity. The method is capable of scaled and exact DCT computation and its associated fast algorithm achieves the theoretical minimal multiplicative complexity for the 8-point DCT. Depending on the nature of the input signal simplifications can be introduced and the overall complexity of the proposed algorithm can be further reduced. Several types of input signal are analyzed: arbitrary, null mean, accumulated, and null mean/accumulated signal. The proposed tool has potential application in harmonic detection, image enhancement, and feature extraction, where input signal DC level is discarded and/or the signal is required to be integrated.

Scalable Approximate DCT Architectures for Efficient HEVC-Compliant Video Coding

An approximate kernel for the discrete cosine transform (DCT) of length 4 is derived from the 4-point DCT defined by the High Efficiency Video Coding (HEVC) standard and used for the computation of DCT and inverse DCT (IDCT) of power-of-two lengths. There are two reasons for considering the DCT of length 4 as the basic module. First, it allows computation of DCTs of lengths 4, 8, 16, and 32 prescribed by the HEVC. Second, the DCTs generated by the 4-point DCT not only involve lower complexity, but also offer better compression performance. Fully parallel and area-constrained architectures for the proposed approximate DCT are proposed to have flexible tradeoff between the area and time complexities. In addition, a reconfigurable architecture is proposed where an 8-point DCT can be used in place of a pair of 4-point DCTs. Using the same reconfiguration scheme, a 32-point DCT could be configured for parallel computation of two 16-point DCTs or four 8-point DCTs or eight 4-point DCTs. The proposed reconfigurable design can support real-time coding for high-definition video sequences in the 8k ultrahigh-definition television format ( $7680\times 4320$ at 30 frames/s). A unified forward and inverse transform architecture is also proposed where the hardware complexity is reduced by sharing hardware between the DCT and IDCT computations. The proposed approximation has nearly the same arithmetic complexity and hardware requirement as those of recently proposed related methods, but involves significantly less error energy and offers better peak signal-to-noise ratio than the others when DCTs of length more than 8 are used. A detailed comparison of the complexity, energy efficiency, and compression performance of different DCT approximation schemes for video coding is also presented. It is shown that the proposed approximation provides a better compressed-image quality than other approximate DCTs. The proposed method can perform HEVC-compliant video coding with marginal degradation of video quality and a slight increase the in bit rate, with a fraction of computational complexity of the latter.

Efficient architecture of variable size HEVC 2D-DCT for FPGA platforms

This study presents a design of two-dimensional (2D) discrete cosine transform (DCT) hardware architecture dedicated for High Efficiency Video Coding (HEVC) in field programmable gate array (FPGA) platforms. The proposed methodology efficiently proceeds 2D-DCT computation to fit internal components and characteristics of FPGA resources. A four-stage circuit architecture is developed to implement the proposed methodology. This architecture supports variable size of DCT computation, including 4×4, 8×8, 16×16, and 32×32. The proposed architecture has been implemented in System Verilog and synthesized in various FPGA platforms. Compared with existing related works in literature, this proposed architecture demonstrates significant advantages in hardware cost and performance improvement. The proposed architecture is able to sustain 4K@30fps ultra high definition (UHD) TV real-time encoding applications with a reduction of 31–64% in hardware cost.

Implementation of computation-reduced DCT using a novel method

The discrete cosine transform (DCT) performs a very important role in the application of lossy compression for representing the pixel values of an image using lesser number of coefficients. Recently, many algorithms have been devised to compute DCT. In the initial stage of image compression, the image is generally subdivided into smaller subblocks, and these subblocks are converted into DCT coefficients. In this paper, we present a novel DCT architecture that reduces the power consumption by decreasing the computational complexity based on the correlation between two successive rows. The unwanted forward DCT computations in each 8 × 8 sub-image are eliminated, thereby making a significant reduction of forward DCT computation for the whole image. This algorithm is verified with various high- and less-correlated images, and the result shows that image quality is not much affected when only the most significant 4 bits per pixel are considered for row comparison. The proposed architecture is synthesized using Cadence SoC Encounter® with TSMC 180 nm standard cell library. This architecture consumes 1.257 mW power instead of 8.027 mW when the pixels of two rows have very less difference. The experimental result shows that the proposed DCT architecture reduces the average power consumption by 50.02 % and the total processing time by 61.4 % for high-correlated images. For less-correlated images, the reduction in power consumption and the total processing time is 23.63 and 35 %, respectively.

VLSI Computational Architectures for the Arithmetic Cosine Transform

The discrete cosine transform (DCT) is a widely-used and important signal processing tool employed in a plethora of applications. Typical fast algorithms for nearly-exact computation of DCT require floating point arithmetic, are multiplier intensive, and accumulate round-off errors. Recently proposed fast algorithm arithmetic cosine transform (ACT) calculates the DCT exactly using only additions and integer constant multiplications, with very low area complexity, for null mean input sequences. The ACT can also be computed non-exactly for any input sequence, with low area complexity and low power consumption, utilizing the novel architecture described. However, as a trade-off, the ACT algorithm requires 10 non-uniformly sampled data points to calculate the eight-point DCT. This requirement can easily be satisfied for applications dealing with spatial signals such as image sensors and biomedical sensor arrays, by placing sensor elements in a non-uniform grid. In this work, a hardware architecture for the computation of the null mean ACT is proposed, followed by a novel architectures that extend the ACT for non-null mean signals. All circuits are physically implemented and tested using the Xilinx XC6VLX240T FPGA device and synthesized for 45 nm TSMC standard-cell library for performance assessment.

OpenCL-based optimization methods for utilizing forward DCT and quantization of image compression on a heterogeneous platform

Recent computer systems and handheld devices are equipped with high computing capability, such as general purpose GPUs (GPGPU) and multi-core CPUs. Utilizing such resources for computation has become a general trend, making their availability an important issue for the real-time aspect. Discrete cosine transform (DCT) and quantization are two major operations in image compression standards that require complex computations. In this paper, we develop an efficient parallel implementation of the forward DCT and quantization algorithms for JPEG image compression using Open Computing Language (OpenCL). This OpenCL-based parallel implementation utilizes a multi-core CPU and a GPGPU to perform DCT and quantization computations. We demonstrate the capability of this design via two proposed working scenarios. The proposed approach also applies certain optimization techniques to improve the kernel execution time and data movements. We developed an optimal OpenCL kernel for a particular device using device-based optimization factors, such as thread granularity, work-items mapping, workload allocation, and vector-based memory access. We evaluated the performance in a heterogeneous environment, finding that the proposed parallel implementation was able to speed up the execution time of the DCT and quantization by factors of 7.97 and 8.65, respectively, obtained from 1024 × 1024 and 2084 × 2048 image sizes in 4:4:4 format.

A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT

Approximation of discrete cosine transform (DCT) is useful for reducing its computational complexity without significant impact on its coding performance. Most of the existing algorithms for approximation of the DCT target only the DCT of small transform lengths, and some of them are non-orthogonal. This paper presents a generalized recursive algorithm to obtain orthogonal approximation of DCT where an approximate DCT of length $N$ could be derived from a pair of DCTs of length $(N/2)$ at the cost of $N$ additions for input preprocessing. We perform recursive sparse matrix decomposition and make use of the symmetries of DCT basis vectors for deriving the proposed approximation algorithm. Proposed algorithm is highly scalable for hardware as well as software implementation of DCT of higher lengths, and it can make use of the existing approximation of 8-point DCT to obtain approximate DCT of any power of two length, $N>8$ . We demonstrate that the proposed approximation of DCT provides comparable or better image and video compression performance than the existing approximation methods. It is shown that proposed algorithm involves lower arithmetic complexity compared with the other existing approximation algorithms. We have presented a fully scalable reconfigurable parallel architecture for the computation of approximate DCT based on the proposed algorithm. One uniquely interesting feature of the proposed design is that it could be configured for the computation of a 32-point DCT or for parallel computation of two 16-point DCTs or four 8-point DCTs with a marginal control overhead. The proposed architecture is found to offer many advantages in terms of hardware complexity, regularity and modularity. Experimental results obtained from FPGA implementation show the advantage of the proposed method.

NON-RECURSIVE COMPUTATION OF 8 × 8 2D DCT FOR HIGH ACCURACY AND LOW AREA

This paper presents non-recursive computation equation for 8 × 8 two-dimensional (2D) discrete cosine transform (DCT) along with novel VLSI architecture for direct computation of DCT without transposition memory. All intermediate operations are performed in non-fraction format. Being non-recursive and all intermediate calculations free of fractions, the proposed architecture has excellent accuracy in terms of peak signal-to-noise ratio (PSNR). The architecture is implemented in 0.18-μm CMOS standard cell technology library and prototyped in Field programmable gate array (FPGA) technology for the silicon validation. Implementation result shows that it has low power consumption and low area as compared to the available architectures of 2D DCT. To further increase the accuracy of computations, hardware overhead is very less as only one register and a multiplier bit-widths need to be changed.

Adaptive discrete cosine transform-based image compression method on a heterogeneous system platform using Open Computing Language

Discrete cosine transform (DCT) is one of the major operations in image compression standards and it requires intensive and complex computations. Recent computer systems and handheld devices are equipped with high computing capability devices such as a general-purpose graphics processing unit (GPGPU) in addition to the traditional multicores CPU. We develop an optimized parallel implementation of the forward DCT algorithm for the JPEG image compression using the recently proposed Open Computing Language (OpenCL). This OpenCL parallel implementation combines a multicore CPU and a GPGPU in a single solution to perform DCT computations in an efficient manner by applying certain optimization techniques to enhance the kernel execution time and data movements. A separate optimal OpenCL kernel code was developed (CPU-based and GPU-based kernels) based on certain appropriate device-based optimization factors, such as thread-mapping, thread granularity, vector-based memory access, and the given workload. The performance of DCT is evaluated on a heterogeneous environment and our OpenCL parallel implementation results in speeding up the execution of the DCT by the factors of 3.68 and 5.58 for different image sizes and formats in terms of workload allocations and data transfer mechanisms. The obtained speedup indicates the scalability of the DCT performance.

Early detection of all-zero [formula omitted] blocks in High Efficiency Video Coding

Similar to previous video coding standards, transform and quantization are employed in the most recent video coding standard High Efficiency Video Coding (HEVC), and there exist a large number of transform coefficients being quantized to zeros. In order to reduce the computations in transform and quantization, a novel prediction algorithm is designed to early detect all-zero 4×4 blocks prior to transform and quantization. A theoretical analysis is performed on the 4×4 Discrete Cosine Transform (DCT) and the related quantization functions in HEVC; consequently, two sufficient conditions to early detect all-zero 4×4 blocks are derived and the proposed prediction algorithm is developed while balancing the detection efficiency and computational overheads. Experimental results demonstrate that the proposed algorithm is able to efficiently predict all-zero 4×4 blocks and reduce redundant DCT and quantization computations while maintaining the same coding performance in terms of video quality and bit rates.

English

We develop an efficient general-purpose blind/no-reference image quality assessment (IQA) algorithm using a natural scene statistics (NSS) model of discrete cosine transform (DCT) coefficients. The algorithm is computationally appealing, given the availability of platforms optimized for DCT computation. The approach relies on a simple Bayesian inference model to predict image quality scores given certain extracted features. The features are based on an NSS model of the image DCT coefficients. The estimated parameters of the model are utilized to form features that are indicative of perceptual quality. These features are used in a simple Bayesian inference approach to predict quality scores. The resulting algorithm, which we name BLIINDS-II, requires minimal training and adopts a simple probabilistic model for score prediction. Given the extracted features from a test image, the quality score that maximizes the probability of the empirically determined inference model is chosen as the predicted quality score of that image. When tested on the LIVE IQA database, BLIINDS-II is shown to correlate highly with human judgments of quality, at a level that is competitive with the popular SSIM index.

A Single-Channel Architecture for Algebraic Integer-Based 8$\,\times\,$8 2-D DCT Computation

An area efficient row-parallel architecture is proposed for the real-time implementation of bivariate algebraic integer (AI) encoded 2-D discrete cosine transform (DCT) for image and video processing. The proposed architecture computes 8 × 8 2-D DCT transform based on the Arai DCT algorithm. An improved fast algorithm for AI-based 1-D DCT computation is proposed along with a single channel 2-D DCT architecture. The design improves on the four-channel AI DCT architecture that was published recently by reducing the number of integer channels to one and the number of eight-point 1-D DCT cores from five down to two. The architecture offers exact computation of 8 × 8 blocks of the 2-D DCT coefficients up to the FRS, which converts the coefficients from the AI representation to fixed-point format using the method of expansion factors. Prototype circuits corresponding to FRS blocks based on two expansion factors are realized, tested, and verified on FPGA-chip, using a Xilinx Virtex-6 XC6VLX240T device. Post place-and-route results show a 20% reduction in terms of area compared to the 2-D DCT architecture requiring five 1-D AI cores. The area-time and area-time <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> complexity metrics are also reduced by 23% and 22% respectively for designs with eight-bit input word length. The digital realizations are simulated up to place and route for ASICs using 45 nm CMOS standard cells. The maximum estimated clock rate is 951 MHz for the CMOS realizations indicating 7.608·10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> pixels/s and a 8 × 8 block rate of 118.875 MHz.

Low-Power High-Modularity Architecture for 8-Point DCT Computation

In this paper, a low-power and high-modularity architecture for 8-point discrete cosine transform (DCT) computation is proposed. The coordinate rotation digital computer (CORDIC) based fast algorithm for DCT computation is derived using matrix decomposition. The sum-angle formula and double-angle formula is used to reduce the CORDIC types. Thus, a high-modularity DCT architecture is obtained by reusing the unique rotation angle CORDIC. The experimental results show that the proposed DCT architecture has lower power and higher modularity than other known architectures.

Characterization of ECG beats from cardiac arrhythmia using discrete cosine transform in PCA framework

Electrocardiogram is the P-QRS-T wave representing the cardiac depolarization and re-polarization, recorded at the body surface. The subtle changes in amplitude and duration of these waves indicate various pathological conditions. It is very difficult to decipher minute changes in the ECG wave by naked eye. Hence a computer aided diagnosis tool to classify various cardiac diseases will assist the doctors in their ECG reading. In this paper, five types of ECG beats (ANSI/AAMI EC57:1998 standard) of MIT–BIH arrhythmia database were automatically classified. Our proposed methodology involves computation of Discrete Cosine Transform (DCT) coefficients from the segmented beats of ECG, which were then subjected for principal component analysis for dimensionality reduction. Then the clinically significant principal components were fed to (i) feed forward neural network, (ii) least square support vector machine with different kernel functions, and (iii) Probabilistic Neural Network (PNN) for automatic classification. We have obtained the highest average sensitivity of 98.69%, specificity of 99.91%, and classification accuracy of 99.52% with the developed knowledge based system. The developed system is clinically ready to deploy for mass screening programs.

Adaptive selection model for detecting zero-quantized discrete cosine transform coefficients in video coding

An adaptive selection approach for advanced video coding that reduces the number of unnecessary discrete cosine transform (DCT), quantization (Q), inverse quantization (IQ), and inverse DCT (IDCT) computations is proposed. An adaptive selection approach is used to detect zero-quantized DCT (ZQDCT) coefficients since certain zero-quantized DCT coefficients of the prediction residual block are difficult to identify. The presented algorithm detects ZQDCT coefficients according to the corresponding frequency positions before implementing DCT. Therefore, redundant DCT, Q, IQ, and IDCT procedures are removed. To carry out the proposed algorithm, three sufficient conditions are assumed for deriving eight prediction modes, which are employed to select various types of DCT, Q, IQ, and IDCT implementations. The computed results indicate that the proposed algorithm is capable of reducing the number of DCT, Q, IQ, and IDCT computations compared to those required by related methods, while retaining the coding performance of the original encoder.

Blind Image Quality Assessment: A Natural Scene Statistics Approach in the DCT Domain

We develop an efficient, general-purpose, blind/noreference image quality assessment (NR-IQA) algorithm using a natural scene statistics (NSS) model of discrete cosine transform (DCT) coefficients. The algorithm is computationally appealing, given the availability of platforms optimized for DCT computation. The approach relies on a simple Bayesian inference model to predict image quality scores given certain extracted features. The features are based on an NSS model of the image DCT coefficients. The estimated parameters of the model are utilized to form features that are indicative of perceptual quality. These features are used in a simple Bayesian inference approach to predict quality scores. The resulting algorithm, which we name BLIINDS-II, requires minimal training and adopts a simple probabilistic model for score prediction. Given the extracted features from a test image, the quality score that maximizes the probability of the empirically determined inference model is chosen as the predicted quality score of that image. When tested on the LIVE IQA database, BLIINDS-II is shown to correlate highly with human judgments of quality, at a level that is competitive with the popular SSIM index.

A simple VLSI architecture for computation of 2D DCT, quantisation and zig-zag ordering for JPEG

In this paper, a comparative simulation study of Peak Signal to Noise Ratio (PSNR) in JPEG image compression is done using two quantisation tables, one recommended by JPEG committee and another suitable for hardware simplification. Simulation results confirm that quantisation table suitable for hardware simplification can be used for designing JPEG baseline encoder circuitry. We present a simple Finite State Machine (FSM)-based VLSI architecture from Discrete Cosine Transform (DCT) to zig-zag reordering of transformed coefficients for JPEG baseline encoder using quantisation table suitable for less complex hardware design. The proposed architecture is implemented in Xilinx FPGA as well as Synopsys DC.

Reconfigurable Architecture for ZQDCT Using Computational Complexity Prediction and Bitstream Relocation

Due to the high computational complexity of discrete cosine transform (DCT) computation, prediction of zero quantized DCT (ZQDCT) coefficients has been extensively studied to reduce the computational complexity of DCT computation. In this letter, we propose a reconfigurable architecture to support ZQDCT computation. Twelve different modes of DCT computations including zonal coding, multiblock processing, and parallel-sequential stage mode can be performed using proposed architecture. We develop a hybrid model-based quality priority algorithm to reduce power consumption, required hardware resources, and computation time with a small quality degradation.

Multiplierless Recursive Algorithm Using Ramanujan Ordered Numbers

A special class of recursive multiplierless transforms for computing Discrete Cosine Transform (DCT) is introduced. DCT computation requires evaluation of cosine angles which are multiples of 2π/N. The proposed algorithm uses Ramanujan ordered number of degree-2 which is represented as 2−1 + 2−m. Thus the cosine functions can be computed by shifts and adds, employing Chebyshev type of recursion. With this algorithm, the floating-point multiplication is completely eliminated, and hence, the multiplierless algorithm can be implemented using shifts and additions only. The orthogonality of the recursive DCT kernel is well maintained through matrix factorization to reduce the computational complexity. The inherent parallel structure yields simpler programming and hardware implementation and provides additions and shifts which is very much less complex when compared to other recent multiplierless algorithms.