Complex Microprocessor Research Articles

The Method of Diversity-Based Ensuring the Reliability of the Router in the IIoT System

The architecture of the Industrial Internet of Things (IIoT) system assumes the presence of a router as the main subsystem, which will allow connecting the subsystems into a single network and connecting them to the equipment of the Internet service provider. Failure of the router can lead to downtime of industrial equipment and the whole workshop at the industrial enterprise, and to the failure of the IIoT system as a whole. Control processing units of industrial routers (RCPU) are complex microprocessor systems (MS). Violation of their operability can be caused by both hardware (HW) and software (SW) failures. Therefore, to increase the reliability of RCPU it is reasonable to use such methods of reliability assurance as HW redundancy (duplication of processors with comparison of results), as well as the use of modern means of control and diagnostics. However, the number of HW and SW failures in RCPUs, is still quite high. In this connection, the solution of issues related to the development of methods for ensuring high reliability of RCPU is of great urgency. This paper proposes a method of ensuring the reliability of RCPU using SW diversity on the basis of priority series. The method let to choose the variant of redundancy of HW and the number of versions of SW as diversity in RCPU.

Silent Data Corruptions: Microarchitectural Perspectives

Today more than ever before, academia, manufacturers, and hyperscalers acknowledge the major challenge of silent data corruptions (SDCs) and aim on solutions to minimize its impact by avoiding, detecting, and mitigating SDCs. Recent studies on large scale datacenters conducted by Meta and Google report an unexpected rate of silent data corruption incidents that are attributed to modern microprocessor generations. Despite the acknowledged severity of the phenomenon, particularly at the datacenter scale, there is no in-depth analysis of the microarchitectural locations in a complex microprocessor that are more likely to generate an SDC at the program outputs. In this paper, we present a detailed analysis of the faulty behavior of many critical microarchitectural structures of a modern out-of-order microprocessor generating silent data corruptions. Our analysis unveils several observations, including: (i) the magnitude of silent data corruptions attributed to different hardware structures, (ii) the instruction-related parameters that are more likely to result in a silent data corruption, (iii) the extent to which the operating system affects the silent data corruption occurrences, and (iv) the byte positions of a word which are more likely to result in silent data corruptions. Collectively, such findings can assist decisions for hardware and software schemes for the reduction of the likelihood of silent data corruptions generation.

Intrinsically disordered proteins SAID1/2 condensate on SERRATE for dual inhibition of miRNA biogenesis in Arabidopsis

Intrinsically disordered proteins (IDPs) SAID1/2 are hypothetic dentin sialophosphoprotein-like proteins, but their true functions are unknown. Here, we identified SAID1/2 as negative regulators of SERRATE (SE), a core factor in miRNA biogenesis complex (microprocessor). Loss-of-function double mutants of said1; said2 caused pleiotropic developmental defects and thousands of differentially expressed genes that partially overlapped with those in se. said1; said2 also displayed increased assembly of microprocessor and elevated accumulation of microRNAs (miRNAs). Mechanistically, SAID1/2 promote pre-mRNA processing 4 kinase A-mediated phosphorylation of SE, causing its degradation invivo. Unexpectedly, SAID1/2 have strong binding affinity to hairpin-structured pri-miRNAs and can sequester them from SE. Moreover, SAID1/2 directly inhibit pri-miRNA processing by microprocessor invitro. Whereas SAID1/2 did not impact SE subcellular compartmentation, the proteins themselves exhibited liquid-liquid phase condensation that is nucleated on SE. Thus, we propose that SAID1/2 reduce miRNA production through hijacking pri-miRNAs to prevent microprocessor activity while promoting SE phosphorylation and its destabilization in Arabidopsis.

A rigorous approach to microprocessor verification using UVM

In today's fast-paced technology industry, microprocessors play an increasingly important role in a wide range of applications. However, verifying the correctness of complex microprocessor designs remains a significant challenge. To address this issue, a rigorous approach to microprocessor verification using the Universal Verification Methodology (UVM) is proposed. UVM provides a standardised and scalable approach to verifying digital designs, including microprocessors, and has been widely adopted in the industry. This research proposes a UVM-based verification framework for microprocessors that can identify and eliminate design errors early in the development cycle. The proposed approach covers functional verification, performance verification, and hardware-software co-verification. The effectiveness of the proposed approach is evaluated through a case study of a commercial microprocessor design, where the UVM-based verification framework successfully detected and resolved several design bugs. The results demonstrate the potential of the proposed rigorous approach to microprocessor verification using UVM to enhance the quality and reliability of microprocessor designs.

Global miRNA dosage control of embryonic germ layer specification

MicroRNAs (miRNAs) have essential functions during embryonic development, and their dysregulation causes cancer1,2. Altered global miRNA abundance is found in different tissues and tumours, which implies that precise control of miRNA dosage is important1,3,4, but the underlying mechanism(s) of this control remain unknown. The protein complex Microprocessor, which comprises one DROSHA and two DGCR8 proteins, is essential for miRNA biogenesis5-7. Here we identify a developmentally regulated miRNA dosage control mechanism that involves alternative transcription initiation (ATI) of DGCR8. ATI occurs downstream of a stem-loop in DGCR8 mRNA to bypass an autoregulatory feedback loop during mouse embryonic stem (mES)cell differentiation. Deletion of the stem-loop causes imbalanced DGCR8:DROSHA protein stoichiometry that drives irreversible Microprocessor aggregation, reduced primary miRNA processing, decreased mature miRNA abundance, and widespread de-repression of lipid metabolic mRNA targets. Although global miRNA dosage control is not essential for mES cells to exit from pluripotency, its dysregulation alters lipid metabolic pathways and interferes with embryonic development by disrupting germ layer specification in vitro and in vivo. This miRNA dosage control mechanism is conserved in humans. Our results identify a promoter switch that balances Microprocessor autoregulation and aggregation to precisely control global miRNA dosage and govern stem cell fate decisions during early embryonic development.

154. Applying Insights from Pri-miRNA Processing to shRNA Design

Short hairpin RNA (shRNA) technology permits efficient and stable gene regulation, providing a useful tool for gene therapy. shRNAs can be embedded in miRNA scaffolds that allow their expression from Pol II promoters, which is more amendable to control transcription. Under this platform, shRNAs are processed through the canonical miRNA maturation pathway, which includes stepwise cleavages by Drosha-DGCR8 complex (Microprocessor) and Dicer. Despite many successes, design of Pol II driven shRNA is far from optimal. Most Pol II driven shRNAs are based on primary transcript sequence of hsa-miR-30a. Recent studies have shown that different pri-miRNAs have distinct Drosha cleavage efficiencies leading to various levels of its mature form. Here, we seek to systematically explore how different pri-miRNA scaffolds can be adapted and optimized to provide the best shRNA expression and function. By taking advantage of DGCR8 KO cells and luciferase-based reporters, we were able to directly monitor Microprocessor cleavage efficiency of primary transcripts in vivo. We have analyzed the Microprocessor cleavage of 20 different primary miRNA transcripts that are the most abundant and widely expressed. Moreover, we have explored how the preservation of stem structure and endogenous surrounding sequences and motifs contribute to shRNA maturation. This study aims to pave the way for a universal miRNA-based shRNA expression platform.

The Design, Simulation, and Performance Characteristics of High Temperature Brushed and Brushless DC Motors, and Their Electronic Controllers

Abstract High temperature brushed and brushless direct current (DC) motors convert electrical energy to mechanical in order to actuate physical systems. This paper is an exploration of these systems from simple designs, which can actuate systems without the use of an electronic controller, to speed or power feedback controlled motors, and finally, to more complex microprocessor controlled systems. The design will review the advantages, disadvantages, specifications, and choice of these motors and their controllers. The simulation will use both Matlab and Spice models to predict the performance characteristics and system stability. And the performance characterization will evaluate measurements of the motors and their electronic control circuits in operation over wide temperature ranges.

DGCR8 HITS-CLIP reveals novel functions for the Microprocessor

The Drosha-DGCR8 complex (Microprocessor) is required for microRNA (miRNA) biogenesis. DGCR8 recognizes the RNA substrate, whereas Drosha functions as the endonuclease. High-throughput sequencing and crosslinking immunoprecipitation (HITS-CLIP) was used to identify RNA targets of DGCR8 in human cells. Unexpectedly, miRNAs were not the most abundant targets. DGCR8-bound RNAs also comprised several hundred mRNAs as well as snoRNAs and long non-coding RNAs. We found that the Microprocessor controls the abundance of several mRNAs as well as of MALAT-1. By contrast, DGCR8-mediated cleavage of snoRNAs is independent of Drosha, suggesting the involvement of DGCR8 in cellular complexes with other endonucleases. Interestingly, binding of DGCR8 to cassette exons, acts as a novel mechanism to regulate the relative abundance of alternatively spliced isoforms. Collectively, these data provide new insights in the complex role of DGCR8 in controlling the fate of several classes of RNAs.

Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures

In this paper, a new fault injection approach to measure SEU sensitivity in COTS microprocessors is presented. It consists in a hardware-implemented module that performs fault injection through the available JTAG-based On-Chip Debugger (OCD). This approach can be applied to most microprocessors, since JTAG standard is a widely supported interface and OCDs are usually available in current microprocessors. Hardware implementation avoids the communication between the target system and the software debugging tool, increasing significantly the fault injection efficiency. The method has been applied to a complex microprocessor (ARM). Experimental results demonstrate the approach is a fast, efficient, and cost-effective solution.

Microfluidic pneumatic logic circuits and digital pneumatic microprocessors for integrated microfluidic systems

We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprocessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner.

Optimizing Thermal Sensor Allocation for Microprocessors

High-performance microprocessor families employ dynamic-thermal-management techniques to cope with the increasing thermal stress resulting from peaking power densities. These techniques operate on feedback generated from on-die thermal sensors. The allocation and the placement of thermal-sensing elements directly impact the effectiveness of the dynamic management mechanisms. In this paper, we propose systematic techniques for determining the optimal locations for thermal sensors to provide high-fidelity thermal monitoring of a complex microprocessor system. Our strategies can be divided into two main categories: uniform sensor allocation and nonuniform sensor allocation. In the uniform approach, the sensors are placed on a regular grid. The nonuniform allocation identifies an optimal physical location for each sensor such that the sensor's attraction toward steep thermal gradients is maximized, which can result in uneven concentrations of sensors on different locations of the chip. We also present a hybrid algorithm that shows the tradeoffs associated with number of sensors and expected accuracy. Our experimental results show that our uniform approach using interpolation can detect the chip temperature with a maximum error of 5.47degC and an average maximum error of 1.05degC . On the other hand, our nonuniform strategy is able to create a sensor distribution for a given microprocessor architecture, providing thermal measurements with a maximum error of 3.18degC and an average maximum error of 1.63degC across a wide set of applications.

Dynamic prediction of architectural vulnerability from microarchitectural state

Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. To protect against soft errors, redundancy techniques such as redundant multithreading (RMT) are often used. However, these techniques assume that the probability that a structural fault will result in a soft error (i.e., the Architectural Vulnerability Factor (AVF)) is 100 percent, unnecessarily draining processor resources. Due to the high cost of redundancy, there have been efforts to throttle RMT at runtime. To date, these methods have not incorporated an AVF model and therefore tend to be ad hoc. Unfortunately, computing the AVF of complex microprocessor structures (e.g., the ISQ) can be quite involved. To provide probabilistic guarantees about fault tolerance, we have created a rigorous characterization of AVF behavior that can be easily implemented in hardware. We experimentally demonstrate AVF variability within and across the SPEC2000 benchmarks and identify strong correlations between structural AVF values and a small set of processor metrics. Using these simple indicators as predictors, we create a proof-of-concept RMT implementation that demonstrates that AVF prediction can be used to maintain a low fault tolerance level without significant performance impact.

Sensitivity guided net weighting for placement-driven synthesis

Net weighting is a key technique in timing-driven placement (TDP), which plays a crucial role for deep submicron very large scale integration of physical synthesis and timing closure. A popular way to assign net weight is based on its slack, such that the worst negative slack (WNS) of the entire circuit may be minimized. While WNS is an important optimization metric, another figure of merit (FOM), defined as the total slack difference compared to a certain slack threshold for all timing end points, is of equal importance to measure the overall timing closure result for highly complex modern application specific integrated circuits and microprocessor designs. Moreover, to optimally assign net weight for timing closure, the effect of net weighting on timing should be carefully studied. In this paper, we perform a comprehensive analysis of the wirelength, slack, and FOM sensitivities to the net weight, and propose a new net weighting scheme based on those sensitivities. Such sensitivity analysis implicitly takes potential physical synthesis effect into consideration. The experiments on a set of industrial circuits show promising results for both stand-alone TDP and physical synthesis afterwards.

Critical Aspects of High-Performance Microprocessor Packaging

AbstractHistorically, the primary function of microprocessor packaging has been to facilitate electrical connectivity of the complex and intricate silicon microprocessor chips to the printed circuit board while providing protection to the chips from the external environment. However, as microprocessor performance continues to follow Moore's law, the package has evolved from a simple protective enclosure to a key enabler of performance. The art and science of semiconductor packaging has advanced radically over the past few decades as faster and more powerful microprocessors with tens of millions of transistors continue to be available, which require more signal and power input/output connections as well as greater power-dissipation capabilities. Key drivers for the development of packaging technologies include power delivery, thermal management, and interconnect scaling, in which the space transformation from fine-featured silicon interconnects to the relatively coarse features seen on motherboards has to be enabled by the package. These drivers, under constant market-driven cost pressure, have led to increased demands on new materials and new package architectures to enable silicon performance. Significant advances have already been made in the areas of heat dissipation, power delivery, high-speed signaling, and high-density interconnects. It is expected that the future evolution of microprocessors will be increasingly challenging in these areas. This article focuses on providing a broad perspective view of the evolution of microprocessor packaging and discusses future challenges.

Electromagnetically driven microactuated device

The micromachining of components from sheets of metal or slices of silicon is used to produce a variety of 3D microcomponents. Microsensors and microactuators are the examples of products that can be combined with integrated circuits (IC) to perform various external functions, such as regulating the flow of gas in an automobile or controlling the temperature and humidity in a large building. Millions of micromachined devices are used in automobiles and in many other mechanical and electronic systems. The future integration of complex micromachined parts with equally complex microprocessor and other IC devices can create cost-effective microelectromechanical systems (MEMS) for many applications in our society. The design, development, and commercialization of cost effective micromachined devices for high volume industrial and consumer applications would be critical in making MEMS technology realize its full potential. The primary requirement for micromachined devices is that they can be manufactured in volume with good cost effectiveness.

Didactical concepts and tools for explaining power electronics applications

Modern power electronics applications are complex microprocessor controlled systems which are very expensive to develop. Assessing and analysing an application before it is built reduces costs and saves development time. Analysing the whole system requires flexible and powerful software tools. In order to analyse applications, a solid education of students is mandatory. For educational purposes especially suited are simulation systems which give students a feeling for power electronics systems and later on are capable of growing and adapting to the gained knowledge of the user. The department of Power Electronics and Electrical Drives at the University of Siegen has developed a software package which is capable of simulating power electronic applications, e.g. electrical drive systems. The simulation system employs modern top-down-design strategies and object-oriented methods to model the application on screen. The application can be simulated in order to gain important data such as dynamic behaviour, load currents, switching frequencies of semiconductors and many more. The system is very useful for teaching the basic concepts of power electronics systems to students or electrical engineers interested in power electronics concepts.