Complex Cache Research Articles

SecurityCloak: Protection against cache timing and speculative memory access attacks

Microarchitectural innovations such as deep cache hierarchies, out-of-order execution, branch prediction and speculative execution in modern processors have made possible to meet ever-increasing demands for performance. However, these innovations have inadvertently introduced vulnerabilities that are exploited by cache-side channel attacks such as Flush & Reload, Prime & Probe, Evict & Time, and attacks such as Spectre and Meltdown that exploit speculative executions. These attacks can potentially leak information which should be secured.Mitigating the attacks while preserving the performance of out-of-order execution has been a challenge. Previous hardware mitigation techniques against cache timing or side-channel attacks include complex cache indexing mechanisms, encrypting addresses, partitioning cache memories, assigning specific ways of a set for each process, or obfuscating cache accesses by using ghost threads. Previous techniques for preventing or at least mitigating attacks based on speculative executions include hiding speculative data accesses using separate buffers or caches, or undoing the effects of speculation throughout program execution. Most techniques address either attacks that exploit speculation such as Spectre or cache side-channel attacks but not both. In many cases, changes to the microarchitecture with additional hardware are needed to implement the security protection. In some cases the mitigations cause performance penalties. In contrast we present very simple designs aimed at preventing both timing based cache side-channel attacks and Spectre style attacks based on speculative executions. Our approach combines obfuscation of cache timing making it more difficult for side-channel attacks to succeed and delaying speculative data accesses that miss in cache until the speculation is resolved. We will show that these approaches prevent both timing attacks such as Flush & Reload, Prime & Probe, Evict & Time as well as speculative attacks such as Spectre. Our technique requires very minimal changes to hardware.

Directed Test Generation for Validation of Cache Coherence Protocols

Computing systems utilize multicore processors with complex cache coherence protocols to meet the increasing need for performance and energy improvement. It is a major challenge to verify the correctness of a cache coherence protocol since the number of reachable states grows exponentially with the number of cores. In this paper, we propose an efficient test generation technique, which can be used to achieve full state and transition coverage in simulation-based verification for a wide variety of cache coherence protocols. Based on effective analysis of the state space structure, our method can generate more efficient test sequences (50% shorter) on-the-fly compared with tests generated by BFS. While our on-the-fly method can reduce the numbers of required tests by half, it can still be impractical to verify all possible transitions in the presence of large number of cores. We propose scalable on-the-fly test generation techniques using quotient state space. The proposed approach guarantees selection of important transitions by utilizing equivalence classes, and omits only similar transitions. Our experimental results demonstrate that our proposed approaches can efficiently tradeoff between transition coverage and validation effort.

Boosting NVDIMM Performance With a Lightweight Caching Algorithm

In the big data era, data-intensive applications have growing demand for the capacity of DRAM main memory, but the frequent DRAM refresh, high leakage power, and high unit cost bring serious design issues on scaling up DRAM capacity. To address this issue, a nonvolatile dual inline memory module (NVDIMM), which is a hybrid memory module, becomes a possible alternative to replace the DRAM as main memory in some data-intensive applications. The NVDIMM that consists of a small-sized high-speed DRAM and a large-sized low-cost nonvolatile memory (i.e., flash memory) has the serious performance issue on accessing data stored in the flash memory because of the huge performance gap between the DRAM and the flash memory. However, there is limited room to adopt a complex caching algorithm for using the DRAM as the cache of flash memory in the NVDIMM main memory, because a complex caching algorithm itself would already cause too much performance degradation on handling each request to access the NVDIMM main memory. In this paper, we present a lightweight caching algorithm to boost NVDIMM performance by minimizing the cache management overhead and reducing the frequencies to access flash memory. A series of experiments was conducted based on popular benchmarks, and the results demonstrate that the proposed algorithm can effectively improve the performance of the NVDIMM main memory.

RACMan: Replication-aware cache management for manycore CMPs with private LLCs

The last level cache (LLC) in private configurations offer lower latency and isolation but extinguishes the possibility of sharing underutilized cache resources. Cooperative Caching (CC) provides capacity sharing by spilling a line evicted from one cache to another. However, CC proposals did not pay enough attention to the natural problem of private LLC, replication. The static policies either indulging the replicated blocks (replicas) in or excluding them out of LLC invariably are deficient for the complex cache capacity situations in manycore environment. In this paper, we present replication-aware cache management (RACMan) to optimize replication for private configurations. RACMan relies on a novel coarse-grained low-overheard mechanism PBFP that monitors and predicts the replica reusability to dynamically adjust LLC insertion policies giving replicas different positions of LRU chain and chances of survival in LLC according to the prediction. Experiment results show our proposal is competent to optimize replication by performing better than two baseline systems in the respects of L2 Hit Rate, Network Traffics, IPC, and Dynamic Energy. RACMan fulfils the requirements of manycore CMPs with private LLC for increasing system performance, area efficiency, and scalability.

Evaluation of HPC Applications’ Memory Resource Consumption via Active Measurement

As the number of compute cores per chip continues to rise faster than the total amount of available memory, applications will become increasingly starved for memory storage capacity and bandwidth, making the problem of performance optimization even more critical. Also, understanding and optimizing the usage of an increasing number of hierarchical memory levels and complex cache management policies is becoming a very hard task. We propose a methodology for measuring and modeling the performance of hierarchical memories in terms of the application’s utilization of the key memory resources: capacity of a given memory level and bandwidth between two levels. This is done by actively interfering with the application’s use of these resources. The application’s sensitivity to reduced resource availability is measured by observing the effect of interference on application performance. The resulting resource-oriented model of performance both greatly simplifies application performance analysis and makes it possible to predict an application’s performance when running with various resource constraints. This is useful to predict performance for future memory-constrained architectures. This paper applies the proposed methodology to six important and well known High Performance Computing (HPC) codes to show the strength and the potential of analysis based on resource-oriented measurements.

An Analytical Model for Loc/ID Mappings Caches

Concerns regarding the scalability of the interdomain routing have encouraged researchers to start elaborating a more robust Internet architecture. While consensus on the exact form of the solution is yet to be found, the need for a semantic decoupling of a node's location and identity is generally accepted as a promising way forward. However, this typically requires the use of caches that store temporal bindings between the two namespaces, to avoid hampering router packet forwarding speeds. In this article, we propose a methodology for an analytical analysis of cache performance that relies on the working-set theory. We first identify the conditions that network traffic must comply with for the theory to be applicable and then develop a model that predicts average cache miss rates relying on easily measurable traffic parameters. We validate the result by emulation, using real packet traces collected at the egress points of a campus and an academic network. To prove its versatility, we extend the model to consider cache polluting user traffic and observe that simple, low intensity attacks drastically reduce performance, whereby manufacturers should either overprovision router memory or implement more complex cache eviction policies.

The load slice core microarchitecture

Driven by the motivation to expose instruction-level parallelism (ILP), microprocessor cores have evolved from simple, in-order pipelines into complex, superscalar out-of-order designs. By extracting ILP, these processors also enable parallel cache and memory operations as a useful side-effect. Today, however, the growing off-chip memory wall and complex cache hierarchies of many-core processors make cache and memory accesses ever more costly. This increases the importance of extracting memory hierarchy parallelism (MHP), while reducing the net impact of more general, yet complex and power-hungry ILP-extraction techniques. In addition, for multi-core processors operating in power- and energy-constrained environments, energy-efficiency has largely replaced single-thread performance as the primary concern. Based on this observation, we propose a core microarchitecture that is aimed squarely at generating parallel accesses to the memory hierarchy while maximizing energy efficiency. The Load Slice Core extends the efficient in-order, stall-on-use core with a second in-order pipeline that enables memory accesses and address-generating instructions to bypass stalled instructions in the main pipeline. Backward program slices containing address-generating instructions leading up to loads and stores are extracted automatically by the hardware, using a novel iterative algorithm that requires no software support or recompilation. On average, the Load Slice Core improves performance over a baseline in-order processor by 53% with overheads of only 15% in area and 22% in power, leading to an increase in energy efficiency (MIPS/Watt) over in-order and out-of-order designs by 43% and over 4.7×, respectively. In addition, for a power- and area-constrained many-core design, the Load Slice Core outperforms both in-order and out-of-order designs, achieving a 53% and 95% higher performance, respectively, thus providing an alternative direction for future many-core processors.

The past is the present and future1: Ambivalent names and naming patterns in post-2000 Zimbabwe

The post-2000 Zimbabwean crisis demonstrates the tendencies and potential in the past to influence the politics of the present. What is widely referred to as the Third Chimurenga (the third liberation struggle) in this crisis epoch is a complex (and at times problematic) cache of nationalist and quasi-nationalist ideologies, philosophies and practices, which are not only connected to the first two Chimurengas through their aspiration for a totally decolonised nation, but also the demand for its political guardianship by the heroes of the armed Second Chimurenga. Many writers have grappled with the hegemonic tendencies of what is now referred to as ‘patriotic history’ (a form of politicised, state-circumscribed history of the nation) without seriously engaging with the deeper crevices of its nature. This paper sets out to argue that in post-2000 Zimbabwean politics, the past and the present are also connected through names and naming patterns that straddle the three Chimurengas with ambivalent meanings and political significance, shaped by spatio-temporal forces peculiar to the historical periods. Comprehending political meanings that such names and nicknames produce in the contexts and circumstances of the three liberation epochs can enhance our understanding of the pre-eminence given to the liberation war's past in contemporary Zimbabwean politics of legitimation and de-legitimation.

An Evaluation of High-Level Mechanistic Core Models

Large core counts and complex cache hierarchies are increasing the burden placed on commonly used simulation and modeling techniques. Although analytical models provide fast results, they do not apply to complex, many-core shared-memory systems. In contrast, detailed cycle-level simulation can be accurate but also tends to be slow, which limits the number of configurations that can be evaluated. A middle ground is needed that provides for fast simulation of complex many-core processors while still providing accurate results. In this article, we explore, analyze, and compare the accuracy and simulation speed of high-abstraction core models as a potential solution to slow cycle-level simulation. We describe a number of enhancements to interval simulation to improve its accuracy while maintaining simulation speed. In addition, we introduce the instruction-window centric (IW-centric) core model, a new mechanistic core model that bridges the gap between interval simulation and cycle-accurate simulation by enabling high-speed simulations with higher levels of detail. We also show that using accurate core models like these are important for memory subsystem studies, and that simple, naive models, like a one-IPC core model, can lead to misleading and incorrect results and conclusions in practical design studies. Validation against real hardware shows good accuracy, with an average single-core error of 11.1% and a maximum of 18.8% for the IW-centric model with a 1.5× slowdown compared to interval simulation.

Region scheduling

The performance of modern many-core platforms strongly depends on the effectiveness of using their complex cache and memory structures. This indicates the need for a memory-centric approach to platform scheduling, in which it is the locations of memory blocks in caches rather than CPU idleness that determines where application processes are run. Using the term 'memory region' to denote the current set of physical memory pages actively used by an application, this paper presents and evaluates region-based scheduling methods for multicore platforms. This involves (i) continuously and at runtime identifying the memory regions used by executable entities, and their sizes, (ii) mapping these regions to caches to match performance goals, and (iii) maintaining region to cache mappings by ensuring that entities run on processors with direct access to the caches containing their regions. Region scheduling can implement policies that (i) offer improved performance to applications by 'unifying' the multiple caches present on the underlying physical machine and/or by 'balancing' cache usage to take maximum advantage of available cache space, (ii) better isolate applications from each other, particularly when their performance is strongly affected by cache availability, and also (iii) take advantage of standard scheduling and CPU-based load balancing when regioning is ineffective. The paper describes region scheduling and its system-level implementation and evaluates its performance with micro-benchmarks and representative multi-core applications. Single applications see performance improvements of up to 15% with region scheduling, and we observe 40% latency improvements when a platform is shared by multiple applications. Superior isolation is shown to be particularly important for cache-sensitive or real-time codes.

Region scheduling

The performance of modern many-core platforms strongly depends on the effectiveness of using their complex cache and memory structures. This indicates the need for a memory-centric approach to platform scheduling, in which it is the locations of memory blocks in caches rather than CPU idleness that determines where application processes are run. Using the term 'memory region' to denote the current set of physical memory pages actively used by an application, this paper presents and evaluates region-based scheduling methods for multicore platforms. This involves (i) continuously and at runtime identifying the memory regions used by executable entities, and their sizes, (ii) mapping these regions to caches to match performance goals, and (iii) maintaining region to cache mappings by ensuring that entities run on processors with direct access to the caches containing their regions. Region scheduling can implement policies that (i) offer improved performance to applications by 'unifying' the multiple caches present on the underlying physical machine and/or by 'balancing' cache usage to take maximum advantage of available cache space, (ii) better isolate applications from each other, particularly when their performance is strongly affected by cache availability, and also (iii) take advantage of standard scheduling and CPU-based load balancing when regioning is ineffective. The paper describes region scheduling and its system-level implementation and evaluates its performance with micro-benchmarks and representative multi-core applications. Single applications see performance improvements of up to 15% with region scheduling, and we observe 40% latency improvements when a platform is shared by multiple applications. Superior isolation is shown to be particularly important for cache-sensitive or real-time codes.

Catherine Mills, Regulation Health and Safety in the British Mining Industries, 1800–1914 (Farnham: Ashgate, 2010), pp. xxv + 284, £60.00, hardback, ISBN: 978-0-7546-6087-3.

Scholars seeking a pathway through the complexities of safety legislation in the British mining industries in the nineteenth and early twentieth centuries have long been in debt to extraordinarily conscientious contemporary and near-contemporary chroniclers of that labyrinthine body of law, no less tortuously convoluted than that governing the railways. There has long been a need for a modern synthesis and interpretation and those have now been provided by Catherine Mills in a study that casts its net wide. Mills engages with the much-overlooked growth of government debate, inspectorates, the actions and inaction of the Home Office, the demographic specifics of occupational health and, by implication, the deep origins of a mid- and later twentieth-century risk society. She deftly simplifies the impenetrably complex or, where she needs to, creatively complicates a bewilderingly complex cache of parliamentary and administrative evidence. Mills locates her study in a now thriving interdisciplinary literature which has its deep origins in Oliver MacDonagh’s work on the growth of government and the early Victorian state, but which has been extended and deepened by political and socio–medical scholars concerned with the history of occupational health and the roles played by the philanthropists, parliamentarians, civil servants and civil scientists, employees and trade unions in the quest for reform. However, this is a clear-eyed, determinedly non-Whiggish, and at times downbeat account. The author touches on the ways in which nineteenth-century print media sensationalised major mining disasters in an effort to hasten reform. Some of these catastrophes are much less well known than others. Thus, in Northumberland and Durham between 1805 and 1819, no fewer than seven major flooding episodes led to the deaths of approximately two hundred and sixty colliers (p. xv). Only one of these accidents killed fewer than thirty men. Mills also gives due attention to collapsing roofs and faulty ladders, and shows how explosions attributable to coal dust and methane contributed to the dismal register of death. But the most compelling part of her argument revolves around ‘invisible’ occupational mortality, most of it attributable to long undifferentiated variants of lung disease. In the earlier nineteenth century, afflicted colliers and workers in the metalliferous sector had a life expectancy at birth comparable to slum-dwellers in Liverpool and Manchester. Half-a-century later, J.S. Haldane concluded that conditions in the Cornish mining industry had deteriorated rather than improved: approximately eight years’ exposure as a machinist in a still, in many respects, pre-industrial working environment would be likely to lead to a premature and horrifically painful death from lung disease (p. 205). Over time, and intensively so between the 1840s and the early 1870s, the public visibility of large-scale disaster and the ‘immorality’ of near-naked workers labouring deep in the bowels of the earth, increased public and parliamentary concern. Owners, radicals believed, must be held either compulsorily, or – classic Victorian legislative evasion – ‘permissively’, to account. In telling pages, Mills describes how helter-skelter mid-century developments – between 1852 and 1854 no fewer than four select committees pondered the operation of the seminal government-backed inspectorial act of 1850 – began to turn the tide in favour of more effective regulation (pp. 99–126). But the metalliferous sector, which employed approximately fifty thousand workers as compared to nearly a quarter-of-a-million labourers in coal mines, lagged badly behind. Small-scale non-ferrous enterprises remained geographically isolated and failed to expand their scale of production. During the final thirty years of the nineteenth century, the sector stagnated in the face of foreign competition, and clung to anciently embedded payment systems based on sub-contracting. A form of pre-industrial individualism and localism proved inimical to the introduction of tougher regulation. In one sense, Mills’s monograph comprises two studies in one (note the plural in the title). Coal mining in Yorkshire and tin mining in Cornwall had about as much in common as chalk and cheese. Nevertheless, the two were repeatedly yoked together in later nineteenth-century administrative discourse and parliamentary debate, and numerous select committees, many of them packed with owners and share-holders deeply opposed to any erosion of permissiveness, sought to extend regulations from one sector to another. Mills’s principal achievement is to have worked her way through a maze of technical, legal, legislative and administrative source material and bring order to chaos. Eschewing explanatory short-cuts, she has made sense of a forbiddingly complicated topic. Discussion of the now half-forgotten growth of government debate, and the role that MacDonagh ascribed – or failed to ascribe – to agency in his original schema becomes repetitious. Nevertheless, this is an impressive synthesis and it is likely to remain essential reading for specialists in the field for a long time to come. One final point: either there has been a printing error or the author deliberately opted to omit any kind of acknowledgement to fellow historians and scholarly labourers at the coalface.

Introduction. Social intelligence: from brain to culture

Humans are perhaps the most social animals. Although some eusocial insects, herd mammals and seabirds live in colonies comprising millions of individuals, no other species lives in such a variety of social groups as Homo sapiens . We live in many different sized societies, from small, nomadic hunter

Parallelizing the Murp Verifier

With the use of state and memory reduction techniques in verification by explicit state enumeration, runtime becomes a major limiting factor. We describe a parallel version of the explicit state enumeration verifier Murp for distributed memory multiprocessors and networks of workstations using the message passing paradigm. In experiments with three complex cache coherence protocols on an Sp2 multiprocessor and on a network of workstations at UC Berkeley, parallel Murp shows close to linear speedups, which are largely insensitive to communication latency and bandwidth. There is some slowdown with increasing communication overhead, for which a simple yet relatively accurate approximation formula is given. Techniques to reduce overhead and required bandwidth and to allow heterogeneity and dynamically changing load in the parallel machine are discussed, which we expect will allow good speedups when using conventional networks of workstations.

Flexible open caching for the Web

Caching plays a vital role in the performance of any large-scale distributed system and, as the variety and number of Web applications grows, is becoming an increasingly important research topic within the Web community. Existing caching mechanisms are largely transparent to their users and cater for resources which are primarily read-only, offering little support for customisable or complex caching strategies. In this paper we examine the deficiencies in these mechanisms with regard to applications with requirements for shared access to data where clients may require a variety of consistency guarantees. We present “open” caching within an object-oriented framework, an approach to solving these problems which, instead of offering caching transparency makes the caching mechanism highly visible allowing great flexibility in caching choices. Our implementation is built upon the W3Objects infrastructure and allows clients to make caching decisions for individual resources with minimal impact upon other resources which do not support our mechanisms.