Complete Optical Receiver Research Articles

A Low-power, CMOS Optical Communication Receiver System for 5Gbps Applications based on RGC Structure

An optical communication receiver system is presented in this research using 65nm CMOS, which consists of three lowpower active differential stages as Limiting Amplifier (LA) following an ultra-low-power RGC-Based Transimpedance Amplifier (RB-TIA). The presented active circuit of the RB-TIA is followed by a gain stage that extends the -3dB frequency of the circuit by creating a resonance for the load capacitance. Thus, needless of consuming extra power, a wide-bandwidth circuit has been designed. In addition, employing active-inductor loads within the LA stages enables obtaining a 5Gbps receiver system. The RB-TIA consumes 573µW and provides 3.52GHz frequency, while the complete optical receiver consumes only 4.76mW power to provide -3dB frequency of 3.5GHz and high gain of 80dB (10’000). The circuits have been mathematically presented and discussed, and simulations have justified the presented circuit design.

Optical receiver front end for optically powered smart dust

SummaryThe ability to create and direct beams of light means that optical communications potentially offer a large power advantage over RF communications for sensor networks. This paper presents an optically powered receiver front end for wireless optical communications. A complete optical receiver front end including a photodetector, clock and Manchester data recovery circuits has been fabricated using the UMC 180 nm CMOS process. A novel modulation scheme is described that has been devised so that this front end can recover the clock and Manchester data from an optical beam. Experimental results show that the total current consumption of the optical receiver front end is as low as 18.8 nA for a 0.5 V supply when a 1 kbps Manchester data and 8 kHz clock signal are successfully recovered. This means that photodiodes on the same substrate as the front end circuits extract enough power from the communications beam to allow the front end to work at distances of up to 10 m from the transmitter. Copyright © 2013 John Wiley & Sons, Ltd.

8 Gbits/s inductorless transimpedance amplifier in 90 nm CMOS technology

This work presents the design and the measured performance of a 8 Gb/s transimpedance amplifier (TIA) fabricated in a 90 nm CMOS technology. The introduced TIA uses an inverter input stage followed by two common-source stages with a 1.5 k? feedback resistor. The TIA is followed by a single-ended to differential converter stage, a differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows a measured optical sensitivity of ?18.3 dBm for a bit error rate = 10?9. A gain control circuitry is integrated with the TIA to increase its input photo-current dynamic range (DR) to 32 dB. The TIA has an input photo-current range from 12 to 500 μA without overloading. The stability is guaranteed over the whole DR. The optical receiver achieves a transimpedance gain of 72 dBΩ and 6 GHz bandwidth with 0.3 pF total input capacitance for the photodiode and input PAD. The TIA occupies 0.0036 mm2 whereas the complete optical receiver occupies a chip area of 0.46 mm2. The power consumption of the TIA is only 12 mW from a 1.2 V single supply voltage. The complete chip dissipates 60 mW where a 1.6 V supply is used for the output stages.

Low-power 10 Gb/s inductorless inverter based common-drain active feedback transimpedance amplifier in 40 nm CMOS

This study presents an inductorless 10 Gb/s transimpedance amplifier (TIA) implemented in a 40 nm CMOS technology. The TIA uses an inverter with active common-drain feedback (ICDF-TIA). The TIA is followed by a two-stage differential amplifier and a 50 Ω differential output driver to provide an interface to the measurement setup. The optical receiver shows measured optical sensitivities of ?17.7 and ?16.2 dBm at BER = 10?12 for data rates of 8 and 10 Gb/s, respectively. The TIA has a simulated transimpedance gain of 47 dBΩ, 8 GHz bandwidth with 0.45 pF total input capacitance for the photodiode, ESD protection and input PAD. The TIA occupies 0.0002 mm2 whereas the complete optical receiver occupies a chip area of 0.16 mm2. The power consumption of the TIA is only 2.03 mW and the complete chip dissipates 17 mW for a 1.1 V single supply voltage. The complete optical receiver has a measured transimpedance gain of 57.5 dBΩ.

Noise performance of a preamplifier for high-speed optical receiver front-ends

This paper reports on an optical receiver employing a p-i-n diode and a GaAs HBT monolithic microwave integrated circuit (MMIC) distributed preamplifier combination. The design is the first to have a photodiode mounted directly on the MMIC chip. The p-i-n preamplifier displays a measured average equivalent input noise current density of 24 pA/Hz. Good agreement is obtained between the predicted and measured noise performance. The monolithic eight-stage distributed amplifier is implemented using Nortels GaAs HBT (fT = 70 GHz) process, and makes use of a coplanar waveguide regime having a large input impedance optimized for noise performance and bandwidth. The p-i-n photodiode employed is an InGaAs vertically illuminated structure, also from Nortel. While the voltage gain of the amplifier displays a 3 dB bandwidth extending to nearly 40 GHz, the bandwidth of the complete optical receiver is found to be only 22 GHz. Packaging effects are believed to be responsible for this shrinkage.

A compact 3R-receiver module for short-haul SDH STM-16 systems

This paper describes a complete 3R optical receiver module for synchronous digital hierarchy (SDH) STM-16 short-haul systems, housed in a 20-pin dual-in-line (DIL) ceramic package. The module includes an InGaAs p-i-n photodiode, a commercial GaAs transimpedance amplifier, and a custom-made silicon bipolar frequency- and phase-locked loop (FPLL)-based clock and data recovery (CDR) circuit. The fiber pigtail is actively aligned to the photodiode by using a proprietary technology that uses a silicon-based optical submount assembly (OSA). The use of a clock recovery circuit based on an FPLL allows avoiding an external low-frequency reference clock and achieving a root-mean square (rms) jitter of 0.075 UI. The module requires two supply voltages of 5 V and -4.5 V, for a total power dissipation of 930 mW, and has a total volume below 0.75 cm/sup 3/ (24.7/spl times/9.9/spl times/3 mm/sup 3/). Measurements have shown full compatibility with SDH standards.

Highly integrated InP HBT optical receivers

This paper presents two highly integrated receiver circuits fabricated in InP heterojunction bipolar transistor (HBT) technology operating at up to 2.5 and 7.5 Gb/s, respectively. The first IC is a generic digital receiver circuit with CMOS-compatible outputs. It integrates monolithically an automatic-gain-control amplifier, a digital clock and data recovery circuit, and a 1:8 demultiplexer, and consumes an extremely low 340 mW of power at 3.3 V, including output buffers. It can realize a full optical receiver when connected to a photo detector/preamplifier front end. The second circuit is a complete multirate optical receiver application-specific integrated circuit (ASIC) that integrates a photodiode, a transimpedance amplifier, a limiting amplifier, a digital clock and data recovery circuit, a 1:10 demultiplexer, and the asynchronous-transfer-mode-compatible word synchronization logic. It is the most functionally complex InP HBT optoelectronic integrated circuit reported to date. A custom package has also been developed for this ASIC.

A GaAs MESFET IC for optical multiprocessor networks

A GaAs, enhanced/depletion mode, self-aligned, refractory-gate, MESFET chip process and circuit family have been developed for the integration of fiber-optic data link functions (e.g. photodetection, amplification, clock recovery, and deserialization) on a single chip. These authors describe the process and present results on integrating a complete optical receiver, including the photodiode and clock recovery circuits, on one chip. The chip functions use over 2000 devices, and perform at 1-GB/s, while dissipating less than 300 mW of heat. This chip is the most complex high-performance optoelectronic integrated circuit reported to date. >