Complementary Source Follower Research Articles

A Wideband Input Buffer Based on Cascade Complementary Source Follower

A Wideband Input Buffer Based on Cascade Complementary Source Follower

Design of a Low-Noise Low-Power Fourth Order Complementary Super Source Follower Filter for EEG Applications

Design of a filter for biomedical application is a challenging task owing to its low-power and low-noise values introduced at low frequencies. This paper describes the design of a Complementary Super Source Follower (CSSF-C) Low Pass Filter (LPF) circuit and the same has been compared with Complementary Source Follower (CSF-C) LPF targeted for the detection of EEG signals. Simulated results obtained in Cadence Analog Design Environment using CMOS 0.18 µm technology node shows the CSSF-C LPF circuit emulates gain of -528 mdB, bandwidth of 100 Hz, power consumption of 12.6 nW from 0.5 V supply voltage. Further, the proposed LPF circuit is capable of achieving Dynamic Range (DR) of 63 dB with an Input Referred Noise (IRN) of 36 µVrms. The proposed CSSF-C LPF is expected to improve the quality of acquired EEG signals.

Ultra-low power signal conditioning system for effective biopotential signal recording

Design of Low-power signal conditioning system comprising of biopotential amplifier (BPA) and low pass Filter (LPF) remains one of the most critical block of system on chips (SoCs) targeted for wearable non-invasive and semi-invasive biomedical applications like electroencephalography and electrocorticography. Design of the same is a challenging task owing to noise-power trade-off in BPA and dependency of process voltage and temperature variations on the filter circuit. We report the design of a signal conditioning system comprising of a capacitively coupled capacitive feedback (CC-CF) BPA and composite p-channel metal oxide semiconductor (PMOS) based complementary source-follower LPF. The results obtained in Cadence with standard 0.18 µm technology and BSIM3V3 MOS models for the proposed signal conditioning system provide a DC-gain value of 36.76 dB, bandwidth of 280 mHz–174 Hz, power consumption of 24.54 µW, supply current of 24.54 µA, area consumption of 0.212826 mm2 from 0.5 V supply voltage. Robustness of this signal conditioning system has been checked by performing 200 runs of monte carlo simulations. The statistical results obtained for gain of (CC-CF) BPA, complementary source follower (CSF-C) LPF and signal conditioning system show mean (µ) values of 39.93 dB, −3.92 dB and 35.96 dB as well as standard deviation () of 135.433 mdB, 1.90 dB, and 2.00 dB respectively. The CC-CF BPA architecture, CSF-C LPF and complete signal conditioning system are expected to be used in SoCs targeted for various low-power biomedical applications.

A Concurrent Dual-band CMOS Partial Feedback LNA with Noise and Input Impedance Matching Optimization for Advanced WLAN Applications

A concurrent dual-band CMOS partial feedback LNA optimizing noise and input reflection coefficient (S<SUB>11</SUB>) at both 2.4 and 5.2 GHz frequency bands is designed using a 65-nm CMOS process for advanced WLAN applications. The inverter-based input transconductance stage directly drives two parallel cascode transistors with 2.4 and 5.2 GHz LC loads, and the output signals splitting into two resonators are combined through a complementary source follower (CSF). Based on an analytical study on the optimum noise impedance (Z<SUB>opt</SUB>) and minimum noise figure (NF<SUB>min</SUB>) of the proposed concurrent LNA circuit topology, the concurrent dual-band input matching network is designed in order to achieve low noise figure (NF) around NF<SUB>min</SUB> at both operating frequencies. By employing a partial resistive feedback between 2.4 GHz LC resonator and input transconductance stage through a CSF, an imperfect S11 of the proposed LNA at 2.4 GHz is improved at the expense of a slight increase of NF. In the simulation, the designed LNA achieved forward gain (S<SUB>21</SUB>) of 14 and 15.5 dB, NF of 1.6 and 2.2 dB, and S11 of -11.2 and -10.3 dB at 2.4 and 5.2 GHz, respectively. The power consumption of the designed LNA is 7.7 mW from a 1.2 V supply voltage.

A 0.3–3.5 GHz active-feedback low-noise amplifier with linearization design for wideband receivers

LNAs for wideband receivers usually require a high linearity to protect the desired signals from out-band interference. Active feedback LNAs always suffer from the nonlinear feedback of source follower, and present a poor linearity. In order to solve this problem, a complementary source follower (CSF) is proposed, which utilizes the different characteristic of NMOS and PMOS to linearize the source follower, leading to an improvement of LNA’s IIP3 and IIP2 by about 10 dBm and 21 dBm respectively. In addition, a post-distortion technique is also used on the common source stage, which further enhances the IIP3 by about 2 dBm and IIP2 by 11 dBm. After using the two techniques, the noise figure (NF) does not deteriorate; instead it achieves a 0.3 dB improvement. A prototype is designed in TSMC 0.18 μm CMOS process, and a 14.8 mW power is dissipated from a 1.6 V supply. In typical process corner, across 0.3 to 3.5 GHz, this LNA achieves a 14.6 dB gain, a 2.9 dB minimum NF, and an IIP2 larger than +22 dBm and IIP3 larger than +1.2 dBm.

A linearized common-gate low-noise amplifier using active cross-coupled feedback technique

A wideband linearized common-gate low-noise amplifier (LNA) is proposed. The linearity is improved by active cross-coupled feedback technique. The active cross-coupled feedback circuit, consisting of a complementary source follower and a feedback capacitor, is employed to enhance loop gain, and acquire linearity improvement. A passive cross-coupled feedback removes the second-order harmonic feedback effect to the input-referred third-order intercept point (IIP3). An enhanced LC-match input network and forward isolation of the active cross-coupled feedback enable the proposed LNA with wideband input matching and flat gain performance, respectively. Fabricated in a 0.13 μm RF CMOS process, the LNA achieves a flat voltage gain of 14.5 dB, an NF of 2.5---3.4 dB, and an IIP3 of 3.1---4.3 dBm over a 3 dB bandwidth of 0.1---1.2 GHz. It consumes only 3.5 mA from a 1.2 V supply and occupies an area of 0.2 mm2.

A +9-dBm Output P1db Active Feedback CMOS Wideband LNA for SAW-Less Receivers

A highly linear complementary source follower (CSF) feedback CMOS wideband LNA is implemented as a part of a highly linear receiver front end resilient to 0-dBm out-of-band blockers. Due to the linear feedback operation of the CSF, the proposed LNA greatly improves large-signal linearity performances compared to the conventional SF feedback LNA. The proposed feedback LNA shows an input P1dB close to 0 dBm while achieving an input reflection coefficient less than -10 dB, an average power gain of 10 dB, and a minimum noise figure of 3 dB. The power consumption is 18 mW at a 2-V supply voltage.

Design of Analog Pixel Memory for Low Power Application in TFT-LCDs

Two types of analog memory cells realized in a 3-μm low temperature polycrystalline silicon (LTPS) technology are proposed to achieve low power application for thin film transistor liquid crystal displays (TFT-LCDs). By employing the inversion signal in the storage capacitor with complementary source follower, the frame rate to refresh the static image can be reduced from 60 to 3.16 Hz with the output decay less than 0.1 V under the input data from 1 to 4 V. To further diminish threshold voltage drop from source follower structure, a compensation technique is implemented to the proposed analog memory cells. In addition, asymmetric output voltage can be also minimized by adding a reference voltage to achieve symmetric output waveform.

P‐40: Design of Analog Pixel Memory Circuit with Low Temperature Polycrystalline Silicon TFTs for Low Power Application

AbstractA new analog pixel memory cell realized in a 3‐μm LTPS technology is proposed to achieve low‐power consumption for TFT‐LCDs. By employing the inversion data in storage capacitor with complementary source follower, the frame rate to refresh the static image can be reduced from 60Hz to 3Hz with output decay only less than 0.075V under the input data from 1V to 4V.

A simple rail‐to‐rail CMOS voltage follower

PurposeThe paper aims to present a simple rail‐to‐rail CMOS voltage follower.Design/methodology/approachThe circuit is developed based on a complementary source follower with a common‐source output stage. The circuit is designed using a 0.13 μm CMOS technology, and operates under the supply voltage of 1.5 V. HSPICE is used to verify the circuit performance.FindingsThe simulations show output voltage swing of ±0.6 V (300 Ω load) with the total harmonic distortion of 0.55 per cent at the operating frequency of 3 MHz. The bandwidth and power dissipation are 657 MHz and 405 μW, respectively.Originality/valueA simple rail‐to‐rail CMOS voltage follower is presented.

A SIMPLE 1.5 V RAIL-TO-RAIL CMOS CURRENT CONVEYOR

A simple 1.5 V rail-to-rail CMOS current conveyor is presented. The circuit is developed based on a complementary source follower with a common-source output stage. The circuit is designed using a 0.13 μm CMOS technology and HSPICE is used to verify the circuit performance. The current conveyor exhibits low impedance at terminal X (7.2 Ω) and can drive ± 0.6 V to the 300 Ω with the total harmonic distortion of 0.55% at the operating frequency of 3 MHz. The voltage transfer error (between the Y and X terminals) and current transfer error (between the X and Y terminals) are small (-0.2 dB). The power dissipation and bandwidth are 532 μW and over 300 MHz, respectively.

Poly-Si TFT push-pull analogue buffer for integrated data drivers of poly-Si TFT-LCDs

A new push-pull analogue buffer for the integrated data driver circuit of polycrystalline silicon (poly-Si) thin-film transistor liquid crystal displays (TFT-LCDs) is proposed. The proposed push-pull analogue buffer is composed of a complementary source follower output stage, a capacitor, and three analogue switches. It has high immunity to the variation of poly-Si TFT characteristics and low power consumption.

2-GHz RF front-end circuits in CMOS/SIMOX operating at an extremely low voltage of 0.5 V

2-GHz RF front-end circuits [low noise amplifier (LNA), mixer, and voltage-controlled oscillator (VCO)] enabling 0.5-V operation are presented. The circuits were fabricated by 0.2-/spl mu/m fully depleted CMOS/SIMOX technology. The mixer has an LC-tuned folded structure to avoid stacking transistors. Undoped-channel MOSFETs are used in the VCO core and in a complementary source follower as output buffers for the mixer and the VCO. The noise figures of 3.5 dB (LNA) and 16.1 dB (mixer), IIP3 of -6-dBm (mixer), and phase noise of -110 dBc/Hz at 1-MHz offset (VCO) are achieved at a supply voltage of 1 V. They dissipate 2 mW (LNA), 4 mW (mixer), and 3 mW (VCO) at 0.5.

Nonlinear performance of the CMOS buffer stages

The nonlinear behaviour of the CMOS buffer stages, the single-stage complementary source follower and the complementary source follower cascade are analysed. Closed-form expressions are obtained for the harmonic and intermodulation components resulting from a multisinusoidal input signal. These expressions can be used to predict the limiting values of the input current for a prespecified tolerable distortion percentage.