Complementary NMOS Research Articles

A complementary high linearity bootstrap switch based on negative voltage bootstrap capacitor

The sample-and-hold (S/H) circuit is an important part of the analog-to-digital converter (ADC). A bootstrap switch with capacitive load can form a basic S/H circuit. A complementary high linearity gate voltage bootstrap switch based on bootstrap capacitor is proposed in this paper. By reducing the size of the key node transistors, the parasitic capacitance is reduced. The sampling metal-oxide-semiconductor field-effect transistor (MOSFET) in this structure is composed of complementary NMOS and PMOS, which reduces the channel charge injection effect and variations in on-resistance (Ron). The simulation results show that the effective number of bits (ENOB), signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the structure are 16.5 bits, 101.11 dB and 101.83 dB respectively at the sampling frequency of 50 MHz and full swing voltage input of 1.8 V based on SMIC 0.18 μm process. Compared with the conventional NMOS switch, ENOB, SDNR, and SFDR are increased by 2.45 bits, 14.73 dB, and 13.38 dB, respectively. In addition, Monte Carlo (MC) and corner simulations of the proposed circuit are performed, and the results show that the proposed circuit has good performance.

Low-power inductorless current-reuse LNAs with active and passive Gm-enhancement

In this paper, two low-power inductorless low-noise amplifiers (LNAs) for multi-standard wireless applications are presented. In the first proposed design, the outputs of two complementary NMOS and PMOS common-gate stages are combined to reduce the power consumption and to facilitate the dc biasing. Also, passive Gm-boosting is applied to the core transistors to improve the noise performance. As a result of these techniques, a minimum NF of 2.6 dB is achieved, while consuming only 1 mA from the 1.8 V supply. In the second proposed design, both active and passive Gm-boosting techniques are applied to the input complementary CG stages to enhance the voltage gain. As a result and by consuming only 1.2 mA, the second LNA achieves a higher voltage gain of 27.9 dB, with the same 3-dB bandwidth.

A Complementary Recycling Operational Transconductance Amplifier with Data-Driven Enhancement of Transconductance

An improved operational transconductance amplifier (OTA) is presented in this work. The fully differential OTA adopts the current recycling technique and complementary NMOS and PMOS input branches to enhance the total transconductance. Moreover, in order to achieve higher current efficiency, a data-driven biasing circuit was developed to dynamically adjust the power consumption of the amplifier. Two comparators were added to detect the voltage difference at the input nodes, and when the differential input is large enough to activate either comparator, extra biasing current is activated and poured into the amplifier to enhance its slew rate and gain-bandwidth product (GBW). The threshold voltage of the complementary recycling folded cascode (CRFC)-based comparator is configured to suppress overshoot. Complementary common-mode feedback (CMFB) topology with local CMFB structure is built to acquire high common-mode gain. The OTA was fabricated in SMIC 0.18- μ m CMOS technology. The experimental result based on a capacitive feedback loop shows that the data-driven operation improves the average slew rate of the amplifier from 10.2 V/ μ s to 55.5 V/ μ s while the power only increases by 150%. The OTA has good potential to satisfy the fast settling demands for capacitive sensing circuits.

A Wideband Noise-Canceling CMOS LNA With Enhanced Linearity by Using Complementary nMOS and pMOS Configurations

A complementary noise-canceling CMOS low-noise amplifier (LNA) with enhanced linearity is proposed. An active shunt feedback input stage offers input matching, while extended input matching bandwidth is acquired by a $\pi$ -type matching network. The intrinsic noise cancellation mechanism maintains acceptable noise figure (NF) with reduced power consumption due to the current reuse principle. Multiple complementary nMOS and pMOS configurations commonly restrain nonlinear components in individual stage of the LNA. Complementary multigated transistor architecture is further employed to nullify the third-order distortion of noise-canceling stage and compensate the second-order nonlinearity of that. High third-order input intercept point (IIP3) is thus obtained, while the second-order input intercept point (IIP2) is guaranteed by differential operation. Implemented in a 0.18- $\mu \text{m}$ CMOS process, the experimental results show that the proposed LNA provides a maximum gain of 17.5 dB and an input 1-dB compression point (IP1 dB) of −3 dBm. An NF of 2.9–3.5 dB and an IIP3 of 10.6–14.3 dBm are obtained from 0.1 to 2 GHz, respectively. The circuit core only draws 9.7 mA from a 2.2 V supply.

A configurable analog buffer dedicated to a wafer-scale prototyping platform

This paper concerns a novel configurable analog buffer dedicated to a wafer-scale prototyping platform of electronic systems. The proposed architecture uses complementary nMOS and pMOS stage buffers, which are built with modified conventional differential pairs used for maximizing the output voltage swing. This compact analog buffer offers several slew-rate features that range from 66 up to 495 V/µs with a quasi-unity gain and only uses 21 transistors for a total silicon area of 0.001824 mm2. The bandwidth of this proposed buffer can be programmed from 74 up to 194 MHz with response time up to 5.3 ns. This overall configurability allows better power management, reduces the power-supply noise injection within the wafer-scale platform, and diminishes the quiescent current.

Low Voltage Low Power Quadrature LC Oscillator Based on Back-gate Superharmonic Capacitive Coupling

This work introduces a new low voltage low power superharmonic capacitive coupling quadrature LC oscillator (QLCO) made by coupling two identical cross-connected LC oscillators without tail transistor. In each of the core oscillators, the back-gate nodes of the cross-coupled NMOS pair and PMOS pair, acting as common mode nodes, have been connected directly. Then the core oscillators are coupled together via capacitive coupling of the PMOS common mode node in one of the core oscillators to the NMOS common mode node in the other core oscillator, and vice versa. Only capacitors are used for coupling of the two core oscillators and therefore no extra noise sources are imposed on the circuit. Operation of the proposed QLCO was investigated with simulation using a commercial 0.18 µm RF CMOS technology: it shows a power dissipation of 5.2 mW from a 0.6 V supply voltage. Since the proposed core oscillator has Complementary NMOS and PMOS cross coupled pairs, and capacitive coupling method will not introduce extra phase noise, so this circuit can operate with a low phase noise as low as −126.8 dBc/Hz at 1 MHz offset from center oscillation frequency of 2.4 GHz, as confirmed with simulation.

A high-order curvature compensation technique for bandgap voltage reference using subthreshold MOSFETs

A bandgap voltage reference with high-order curvature compensation is presented in this study. It exploits subtraction and derivative equalisation of currents generated from two complementary NMOS and PMOS bandgap references (BGRs) using subthreshold MOSFETs. By equating the derivative with respect to temperature of the two currents, generated by the complementary bandgaps, and subtracting these currents, an accurate high-order curvature compensation is achieved. To overcome problems due to the limited input common-mode range of opamps used in BGRs, a transimpedance amplifier with new accurate current compensation that tracks the temperature variation is proposed. This bandgap is implemented using the 0.18 μm CMOS process with a supply voltage as low as 0.7 V. At 0.8 V power supply and an output reference voltage of 386 mV, the proposed circuit achieves a temperature coefficient of 19 ppm/°C from 0 to 130°C. The power consumption is 119 μW and the power supply reduction ratio is 24 dB at 1 kHz.

Design of a CMOS opamp input stage immune to EMI

In this paper the behaviour of a complementary nMOS–pMOS differential pair in the presence of RF interference superimposed on the input terminals is analysed. An intrinsic nonlinearity cancellation mechanism in this structure is demonstrated, and proper design criteria are presented to exploit this mechanism in order to achieve a very high immunity to RF interference. A high-immunity complementary differential pair has been employed as an input stage of a folded cascode operational amplifier and its improved behaviour in the presence of RF interference has been verified by computer simulations.

Pass-transistor adiabatic logic using single power-clock supply

We present a new pass-transistor adiabatic logic (PAL) that operates from a single power-clock supply and outperforms the previously reported adiabatic logic techniques in terms of its energy use. PAL is a dual-rail logic with relatively low gate complexity: a PAL gate consists of true and complementary NMOS functional blocks, and a pair of cross-coupled PMOS devices. In simulation tests using a standard 1.2 /spl mu/ CMOS technology, the circuit has been found to operate up to 160 MHz clock frequency and down to 1.5 V peak-to-peak sinusoidal power-clock supply. Operation of a 1600-stage PAL shift register fabricated in the 1.2 /spl mu/ CMOS technology has been experimentally verified.