In this study, three major reliability aspects, hot carrier effects, latch-up and electrostatic discharge (ESD) have been simultaneously studied on a 0.25 μm complementary metal-oxide silicon (CMOS) technology. For this purpose, three source–drain architectures large angle tilted implementation drain (LATID, MDD, Abrupt) processed on different kinds of substrate (bulk and epitaxial ones) are compared with respect to these three reliability aspects. This work clearly demonstrates the dependence existing between them. The source–drain architecture affects, of course, the hot carrier reliability but also the ESD performances. A thinner epitaxial substrate is effective in reducing latch-up occurrences, but degrades the ESD failure threshold. Consequently, global technology optimisation will be a trade off between these various reliability aspects.