CMOS Research Articles

Fabrication of Ultrathin Ferroelectric Al0.7Sc0.3N Films under Complementary-Metal-Oxide-Semiconductor Compatible Conditions by using HfN0.4 Electrode.

Aluminum scandium nitride (AlScN) has emerged as a promising candidate for next-generation ferroelectric memories, offering a much higher remanent charge density than other materials with a stable ferroelectric phase. However, the inherently high coercive field requires a substantial decrease in film thickness to lower the operating voltage. Significant leakage currents present a severe challenge during the thickness scaling, especially when maintaining compatibility with complementary-metal-oxide-semiconductor (CMOS) fabrication standards. This study adopts a HfN0.4 bottom electrode, which minimizes lattice mismatch with Al0.7Sc0.3N (ASN), forming a coherent bottom interface that effectively reduces leakage currents even at thickness <5nm. CMOS-compatible HfN0.4/ASN/TiN stack, deposited without vacuum break between each layer, demonstrates exceptional scalability, confirming the ferroelectricity of ASN films at thicknesses down to 3nm. The coercive voltage is decreased to 4.35V, significantly advancing low-voltage AlScN devices that align with CMOS standards.

High-speed voltage level-up shifter with wide range conversion for system-on-chip applications

Abstract The purpose of this investigation is to demonstrate a level shifter circuit that enhances voltage switching capacity while simultaneously reducing latency by employing a cascaded current mirror, input, and output inverters. We improved our design using multi-threshold Complementary metal oxide semiconductor (MTCMOS) technology by adding stackable transistors, super-cutoff mechanisms, and cascaded techniques. The level shifting between voltage ranges of 0.3 V and 2.0 V is accomplished by the proposed level shifter. Our design has been fine-tuned to meet the needs of system-on-chip applications by meticulously optimizing performance characteristics like energy usage, latency, and space utilization. The proposed level shifter has an area of 6.936 µm2 and a power consumption of 17 nW, with a delay of 90.64 ps. The proposed work has been done on the Cadence Virtuoso Tool using 45 nm technology. Our suggested level shifter is more effective than earlier methods in terms of latency and conversion range. In addition to delivering considerable reductions in space and power consumption, the suggested design promises a 50-fold increase in operating speed.&amp;#xD;

Triple-Stacked FET Distributed Power Amplifier Using 28 nm CMOS Process

A broadband 28 nm complementary metal–oxide–semiconductor (CMOS) power amplifier was implemented using a distributed amplification design. To develop a model library for high-frequency design, various test patterns for active and passive elements were fabricated and compared through measurements. As a result, a symmetrical n-channel field-effect transistor (NFET) was used as the active device, and a co-planar waveguide (CPW) with floating bottom metal layers was chosen as the transmission line for the passive element. These choices demonstrated superior radio frequency (RF) characteristics at high frequencies compared to other device candidates. Furthermore, to address the low breakdown voltage of CMOS, a triple-stacked FET structure was designed as the gain cell of the distributed power amplifier (DPA). The fabricated DPA showed a maximum small-signal gain of 22 dB and a minimum of 10 dB from DC to 56 GHz, with a maximum saturated output power of 20 dBm and a minimum of 13 dBm from 1 to 39 GHz. Notably, these results were achieved on the first attempt by designing solely based on measurement data from the test patterns.

High performance Si-MoS2 heterogeneous embedded DRAM.

Embedded Dynamic RAM (eDRAM) has become a key solution for large-capacity cache in high-performance processors. A heterogeneous two transistor capacitorless eDRAM (2T-eDRAM) that combines silicon and molybdenum disulfide (MoS2) is reported to address the short retention issue in conventional gain cell (GC) eDRAMs meanwhile eliminate the pillar capacitor in one transistor and one capacitor (1T1C) eDRAMs. The MoS2 write transistor with low OFF current (IOFF) enables long data retention, while the Si read transistor offers high drive current and logic compatibility. This combination enhances data retention by 1000 times and sense margin by 100 times respectively compared to full Si and MoS2 counterparts. A three-dimensional (3D) design stacking MoS2 on Si is demonstrated with back-end-of-line (BEOL) process to double integration density. With 6000 s data retention, 35 μA/μm sense margin, 5 ns access speeds, 3D integration and CMOS logic compatibility, this Si-MoS2 eDRAM marks a significant advancement in memory technology.

Near‐Infrared Dual‐Band Frequency Comb Generation from a Silicon Resonator

AbstractBenefitting from the mature, cost‐effective, and scalable manufacturing capabilities of complementary metal‐oxide‐semiconductor (CMOS) technology, silicon photonics has facilitated the seamless and monolithic integration of diverse functionalities, including optical sources, modulators, and photodetectors. Microresonators can generate multiple coherent optical frequency comb lines and serve as optical sources. However, at the telecom band, silicon suffers from two‐photon absorption and free‐carrier absorption, which severely hampers the realization of microcombs from a single silicon chip at telecom wavelengths until now. In this paper, a novel approach is presented and demonstrated with near‐infrared dual‐band frequency combs from a multimode silicon resonator. With a single pumping configuration, dual‐band combs are generated from the interaction between the pump and Raman Stokes fields by involving two different optical mode families but with similar group velocities. It is observed that the pump power required to generate dual‐band combs is as low as 0.7 mW. The work in bringing telecom microcombs to the silicon platform will advance silicon photonics for the next generation of monolithically integrated technology based on a single silicon chip, enabling new possibilities for further exploring silicon photonics‐based applications in optical telecommunications, sensing, and quantum metrology in the telecom band using a monolithic single silicon chip.

Monolithically Integrated Quantum Dots in a 22‐nm Fully Depleted Silicon‐on‐Insulator Process Operating at 3 K

ABSTRACTQuantum computers comprising large‐scale arrays of qubits will enable complex algorithms to be executed to provide a quantum advantage for practical applications. A prerequisite for this milestone is a power‐efficient qubit control and detection system operating at cryogenic temperatures. Implementing such systems in complementary metal‐oxide‐semiconductor (CMOS) technology offers clear advantages in terms of scalability. Here, we present a fully integrated quantum dot array in which silicon quantum wells are co‐located with control and detection circuitry on the same die in a commercial 22‐nm fully depleted silicon‐on‐insulator (FDSOI) process. Our system comprises a two‐dimensional quantum dot array, integrated with 8 detectors and 32 injectors, operating at 3 K inside a cryo‐cooler. The power consumption of the control and detection circuitry is 2.5 mW per qubit without body biasing. The design utilizes 0.8‐V nominal devices. The setup allows us to verify discrete charge injection control and detection at the quantum dot array and demonstrate the feasibility of this architecture for scaling up the existing quantum core to hundreds and thousands of physical qubits.

Analysis of SiNx Waveguide-Integrated Liquid Crystal Platform for Wideband Optical Phase Shifters and Modulators

In this study, the potential of employing SiNx (silicon nitride) waveguide platforms to enable the use of liquid-crystal-based phase shifters for on-chip optical modulators was thoroughly investigated using 3D-FDTD (3D finite-difference time-domain) simulations. The entire structure of liquid-crystal-based Mach–Zehnder interferometer (MZI) optical modulators, consisting of multi-mode interferometer splitters, different tapering sections, and liquid-crystal-based phase shifters, was systematically and holistically investigated with a view to developing a compact, wideband, and CMOS-compatible (complementary metal-oxide semiconductor) bias voltage optical modulator with competitive modulation efficiency, good fabrication tolerance, and single-mode operation using the same SiNx waveguide layer for the entire device. The trade-off between several important parameters is critically discussed in order to reach a conclusion on the possible optimized parameter sets. Contrary to previous demonstrations, this investigation focused on the potential of achieving such an optical device using the same SiNx waveguide layer for the entire device, including both the passive and active regions. Significantly, we show that it is necessary to carefully select the phase shifter length of the LC-based (liquid crystal) MZI optical modulator, as the phase shifter length required to obtain a π phase shift could be as low as a few tens of microns; therefore, a phase shifter length that is too long can contradictorily worsen the optical modulation.

Fully integrated multi-mode optoelectronic memristor array for diversified in-sensor computing.

In-sensor computing, which integrates sensing, memory and processing functions, has shown substantial potential in artificial vision systems. However, large-scale monolithic integration of in-sensor computing based on emerging devices with complementary metal-oxide-semiconductor (CMOS) circuits remains challenging, lacking functional demonstrations at the hardware level. Here we report a fully integrated 1-kb array with 128 × 8 one-transistor one-optoelectronic memristor (OEM) cells and silicon CMOS circuits, which features configurable multi-mode functionality encompassing three different modes of electronic memristor, dynamic OEM and non-volatile OEM (NV-OEM). These modes are configured by modulating the charge density within the oxygen vacancies via synergistic optical and electrical operations, as confirmed by differential phase-contrast scanning transmission electron microscopy. Using this OEM system, three visual processing tasks are demonstrated: image sensory pre-processing with a recognition accuracy enhanced from 85.7% to 96.1% by the NV-OEM mode, more advanced object tracking with 96.1% accuracy using both dynamic OEM and NV-OEM modes and human motion recognition with a fully OEM-based in-sensor reservoir computing system achieving 91.2% accuracy. A system-level benchmark further shows that it consumes over 20 times less energy than graphics processing units. By monolithically integrating the multi-functional OEMs with Si CMOS, this work provides a cost-effective platform for diverse in-sensor computing applications.

Research on real-time 3D imaging technology based on CMOS sensors

Abstract. With the continuous progress of science and technology, 3D imaging technology has been widely used in many fields, such as medical imaging, virtual reality and protection of cultural heritage. It can provide more information than traditional 2D images, greatly improving the accuracy and reliability of various applications. CMOS (Complementary Metal Oxide Semiconductor) sensors, as efficient and low-cost image sensors, have been widely used in image imaging and processing technologies in recent years. However, how to realize real-time and high-precision 3D imaging with CMOS sensors is still a technical challenge to be solved. Based on this background, this paper will focus on real-time 3D imaging techniques based on CMOS sensors through three topics. This paper will first introduce how CMOS sensors work, followed by the introduction of real-time 3D imaging technology, and finally the real-time 3D imaging technology based on CMOS sensors. The research in this paper will be valuable for the research and application of real-time 3D imaging technology based on CMOS sensors.

Lateral Mn5Ge3 spin-valve in contact with a high-mobility Ge two-dimensional hole gas

Abstract Ge two-dimensional hole gases (2DHG) in strained modulation-doped quantum-wells represent a promising material platform for future spintronic applications due to their excellent spin transport properties and the theoretical possibility of efficient spin manipulation. Due to the continuous development of epitaxial growth recipes extreme high hole mobilities and low effective masses can be achieved, promising an efficient spin transport. Furthermore, the Ge 2DHG can be integrated in the well-established industrial complementary metal-oxide-semiconductor (CMOS) devices technology. However, efficient electrical spin injection into a Ge 2DHG—an essential prerequisite for the realization of spintronic devices—has not yet been demonstrated. In this work, we report the fabrication and low-temperature magnetoresistance (MR) measurements of a laterally structured Mn5Ge3/Ge 2DHG/ Mn5Ge3 device. The ferromagnetic Mn5Ge3 contacts are grown directly into the Ge quantum well by means of an interdiffusion process with a spacing of approximately 130 nm, forming a direct electrical contact between the ferromagnetic metal and the Ge 2DHG. Here, we report for the first time a clear MR signal for temperatures below 13 K possibly arising from successful spin injection into the high mobility Ge 2DHG. The results represent a step forward toward the realization of CMOS compatible spintronic devices based on a 2DHG.

Precise p-type and n-type doping of two-dimensional semiconductors for monolithic integrated circuits

The controllable fabrication of patterned p-type and n-type channels with precise doping control presents a significant challenge, impeding the realization of complementary metal-oxide-semiconductor (CMOS) logic using a single van der Waals material. However, such an achievement could offer substantial benefits by enabling continued transistor scaling and unprecedented interlayer interconnect technologies. In this study, we devise a precise method for two-dimensional (2D) semiconductor substitutional doping, which allows for the production of wafer-scale 2H-MoTe2 thin films with specific p-type or n-type doping. Notably, we extend this approach to the synthesis of spatially selective doped 2H-MoTe2 thin films via a one-step growth method, facilitating the monolithic integration of p-type and n-type semiconductor channels. Leveraging this advancement, we successfully fabricate a chip-sized 2D CMOS inverter array that demonstrates excellent device performance and yield. Collectively, these findings represent a significant stride towards the practical incorporation of 2D semiconductors in very large-scale integration technology.

FDM‐Printed CMOS Logic Gates from Flexing Beam Mechanisms for the Control of Soft Robotic Systems

FDM‐Printed CMOS Logic Gates from Flexing Beam Mechanisms for the Control of Soft Robotic Systems

Surface-modified CMOS biosensors

Biosensors translate biological events into electronic signals that quantify biological processes. They are increasingly used in in vitro diagnostics applications that leverage their ability to process small sample volumes. One recent trend has been to integrate biosensors with complementary metal-oxide-semiconductor (CMOS) chips to provide enhanced miniaturization, parallel sensing, and low power consumption at a low cost. CMOS-enabled biosensors are used in monitoring DNA hybridization, enzymatic reactions, and cell proliferation, to name a few applications. This paper explores the materials and processes used in emerging CMOS biosensors. We discuss subtractive and additive processes for creating electrodes for electrochemical sensing applications. We discuss functionalization techniques for creating bioelectronic interfaces that allow molecular events to be transduced into the electrical domain using a plurality of modalities that are readily provided by CMOS chips. Example modalities featured are optical sensing, electrochemical detection, electrical detection, magnetic sensing, and mechanical sensing.

Ultra-compact on-chip camera based on optoelectronic compound eyes with nonuniform ommatidia

Abstract Compound eyes (CEs) that feature ultra-compact structures and extraordinary versatility have revealed great potential for cutting-edge applications. However, the optoelectronic integration of CEs with available photodetectors is still challenging because the planar charge-coupled device (CCD)/complementary metal oxide semiconductor (CMOS) detector cannot match the spatially distributed images formed by CE ommatidia. To reach this end, we report here the optoelectronic integration of CEs by manufacturing 3D nonuniform ommatidia for developing an ultra-compact on-chip camera. As a proof-of-concept, we fabricated microscale CEs with uniform and nonuniform ommatidia through femtosecond laser two-photon photopolymerization, and compared their focusing/imaging performance both theoretically and experimentally. By engineering the surface profiles of the ommatidia at different positions of the CE, the images formed by all the ommatidia can be tuned on a plane. In this way, the nonuniform CE can be directly integrated with a commercial CMOS photodetector, forming an ultra-compact CE camera. Additionally, we further combine the CE camera with a microfluidic chip, which can further serve as an on-chip microscopic monitoring system. We anticipate that such an ultra-compact CE camera may find broad applications in microfluidics, robotics, and micro-optics.

Neuronal Multi Unit Activity Processing with Metal Oxide Memristive Devices

AbstractIntra‐cortical brain‐machine interfaces (BMIs), able to decode neural activity in real‐time, represent a revolutionary opportunity for treating medical conditions. However, traditional systems focusing on single‐neuron spike detection require high processing rates and power, hindering the up‐scaling for neurons‐population monitoring in clinical application. An intriguing proposition is the memristive integrating sensor (MIS) approach, which uses resistive RAM (RRAM) for threshold‐based neural activity detection. MIS leverages analogue multi‐state switching properties of metal‐oxide RRAM to compress neural inputs by encoding above‐threshold events in resistance displacement, facilitating efficient data down‐sampling in the post‐processing, enabling low‐power, high‐channel systems. Initially tested on spikes and local field potentials, here MIS is adapted to process multi‐unit activity envelope (eMUA)—the envelope of entire spiking activity—which has recently been proposed as crucial input for real‐time neuro‐prosthetic control. Prior necessary modifications to the MIS for effective operation, this adaptation achieved over 95% sensitivity across two types of metal‐oxide devices: Pt/TiOx/Pt and TiN/HfOx/TiN, proving its platform‐agnostic capabilities. Furthermore, towards the integration of MIS with silicon chips, it is shown that it can reduce total system power consumption to below 1 µW, as RRAM encoding stage relaxes the signal preservation and noise requirements that challenge traditional complementary metal‐oxide‐semiconductor (CMOS) front‐ends. This eMUA‐MIS adaptation offers a viable pathway for developing more scalable and efficient BMIs for clinical use.

Development of a DualEmission Laser-Induced Fluorescence (DELIF) Method for Long-Term Temperature Measurements

The fluorescence intensity of fluorescent dyes typically employed in the dual-emission laser-induced fluorescence (DELIF) method gradually degrades as the excitation time increases, and the degradation rate depends on the type of fluorescent dye used. Therefore, the DELIF method is unsuitable for long-term temperature measurements. In this study, we focused on the fluorescence intensity ratio of a single fluorescent dye at two fluorescence wavelengths and developed a DELIF method for long-term temperature measurements based on this ratio. The fluorescence intensity characteristics of Fluorescein disodium and Rhodamine B, which are typically used in the DELIF method, in the temperature range of 10–60 °C were comprehensively investigated using two high-speed monochrome complementary metal-oxide semiconductor cameras and narrow bandpass filters. Interestingly, the ratio of the fluorescence intensity of each fluorescent dye at the peak emission wavelength of the fluorescence spectrum, λ, to the fluorescence intensity at wavelengths very close to the peak wavelength (λ ± 10 nm) was highly sensitive to temperature variations but not excitation time. Particularly, when Rhodamine B was used, the selection of the fluorescence intensity ratios at a wavelength combination of 589 and 600 nm enabled highly accurate temperature measurements with a temperature resolution of ≤0.042 °C. Moreover, the fluorescence intensity ratio varied negligibly throughout the excitation time of 180 min, with a measurement uncertainty (95% confidence interval) of 0.045 °C at 20 °C. The results demonstrate that the proposed DELIF method enables highly accurate long-term temperature measurements.

H-BN-assisted-transferred metal contacts to InSe for twodimensional multifunctional electronic devices

Abstract Metal contacts to two-dimensional semiconductors play a crucial role in determining the electrical performance of the electronic devices. However, traditional three-dimensional metal deposition processes will bring damage to two-dimensional semiconductors and cause significant Fermi-level-pinning effects. In this work, we report a hexagonal boron nitride (h-BN)-assisted-transferred method for metal contacts to few-layered InSe for construction of two-dimensional functional electronic devices. Using transferred Pt electrodes as the contact, p-type dominated ambipolar conduction behavior with the hole Schottky barrier height (SBH) approaching 0 meV was observed in field-effect transistors (FETs) based on multilayered InSe. Based on this, using a dual-gate modulating method, multiple types of InSe homojunctions, including p-p, n-n, p-n and n-p junctions, could be constructed. For InSe p-n homojunctions, a current rectification ratio of over 104 and optoelectronic detection capabilities were achieved. Furthermore, a complementary metal-oxide-semiconductor (CMOS) inverter with an ultra-high voltage gain exceeding 60 at VDD = -1 V was constructed. Our h-BN-assistedtransferred metal contact method can be easily extended to other two-dimensional semiconductors for the construction of complementary electronic and optoelectronic devices.

Energy-efficient design and CNFET implementation of GDI-based ternary prefix adders

Abstract Ternary adders have produced more benefits compared to binary adders i.e., the ternary adder occupies less amount of area as well as produces less interconnect complexity. However, the CMOS implementation of the ternary adders failed to perform the process when the channel length was taken as 32 nm. At 32 nm technology, the CMOS transistors exhibit undesired effects such as Short Channel Effects (SCEs), mobility degradation, high leakage current, etc. Multi-gate devices are preferred to overcome these issues. Carbon Nano-tube Field Effect Transistors (CNFETs) are one of the technologies to work efficiently when the channel length is 32 nm. In this paper, CNFET-based ternary prefix adders are designed. Power consumption is the most critical requirement for the VLSI system, as it enhances energy efficiency and reduces heat dissipation. One way to achieve this power reduction is by minimizing the number of transistors employed in the adder circuits. This study employed a reduction technique known as Gate Diffusion Input (GDI) logic included in the proposed prefix adder design. The overall experimental investigation is done with the help of the HSPICE supporting platform. The proposed adder improved by reducing the power by up to 83%, energy by up to 83%, current by up to 78%, and delay by up to 96%. Finally, the Power Delay product (PDP) was also reduced by 84% compared to existing ternary adders. The proposed design proves to be highly effective in implementing the neuron structure, with the corresponding parameters thoroughly analysed and well-documented in this study.

Modified Si Oxidation Behavior by Ultrathin Ni Catalyst Enabling Oxidant-Less Metal-Assisted Chemical Etching.

Metal-assisted chemical etching (MACE), a wet-based anisotropic etching process for semiconductors, has emerged as an alternative to plasma-based etching. However, using noble metal catalysts in MACE limits the implementation of complementary metal-oxide-semiconductor (CMOS) processes. This study explores Si etching using an ultrathin Ni catalyst as a novel approach for MACE. The thickness of the Ni catalyst emerges as a critical parameter, with 1 nm of Ni proving to be the optimal thickness to achieve smooth and deep etching. Unlike conventional MACE methods, the ultrathin Ni catalyst enables Si etching without strong oxidants. Wafer-scale Si etching demonstrates the versatility of the ultrathin Ni catalyst in producing various microstructures. It is found that the ultrathin Ni/Si interfacial state plays a crucial role in influencing the Si reactivity, lowering the barrier for Si oxidation. CMOS-compatible and cost-efficient ultrathin Ni makes MACE a promising alternative for semiconductor nanofabrication. This study pioneers MACE using an ultrathin non-noble metal catalyst, offering valuable insights for researchers in this field.

Effects of Thickness and Anisotropic Strain on Polarization Switching Properties of Sub-10nm Epitaxial Hf0.5Zr0.5O2 Thin Films

Abstract Doped HfO2-based ferroelectric (FE) films are emerging as leading contenders for next-generation FE non-volatile memories due to their excellent compatibility with complementary metal oxide semiconductor processes and robust ferroelectricity at nanoscale dimensions. Despite the considerable attention paid to the FE properties of HfO2-based films in recent years, enhancing their polarization switching speed remains a critical research challenge. We demonstrate the strong ferroelectricity of sub-10 nm Hf0.5Zr0.5O2 (HZO) thin films and show that the polarization switching speed of these thin films can be significantly affected by HZO thickness and anisotropically strained La0.67Sr0.33MO3-buffered layer. Our observations indicate that the HZO thin film thickness and anisotropically strained La0.67Sr0.33MO3 layer influence the nucleation of reverse domains by altering the phase composition of the HZO thin film, thereby reducing the polarization switching time. Although the increase in HZO thickness and anisotropic compressive strain hinder the formation of the FE phase, they can enable faster switching. Our findings suggest that FE HZO ultrathin films with polar orthorhombic structures have broad application prospects in microelectronic devices. These insights into novel methods for increasing polarization switching speed are poised to advance the development of high-performance FE devices.