Complementary Metal Oxide Semiconductor Circuitry Research Articles

A review of silicon carbide CMOS technology for harsh environments

A comprehensive overview of the advancements, challenges, and prospects of silicon carbide (SiC) complementary metal-oxide-semiconductor (CMOS) technology is presented. As the demand for high-performance and energy-efficient electronic devices continues to grow, SiC has emerged as a promising material due to its unique properties. The paper aims to provide a thorough understanding of the state-of-the-art developments in SiC CMOS technology. The paper delves into the key features of SiC and its compatibility with CMOS processing techniques. It highlights the challenges associated with SiC CMOS technology, such as substrate quality, interface states, and process integration. Examples of CMOS circuitry that have been successfully designed, fabricated, and tested are provided.

An Ultra-Thin Ultraviolet Enhanced Backside-Illuminated Single-Photon Avalanche Diode With 650 nm-Thin Silicon Body Based on SOI Technology

We present the world's thinnest backside illuminated (BSI) single-photon avalanche diode (SPAD) with a silicon (Si) thickness of 650 nm fabricated in complementary metal-oxide-semiconductor (CMOS) compatible silicon-on-insulator (SOI) technology. The well-optimized doping profile is exploited in this square-shaped BSI SPAD with ultrathin Si body consisting of n^{++}/p-well and n-well guard ring (GR) to outstandingly improve detection efficiency in ultraviolet (UV) spectral range. This BSI SPAD exhibits a low leakage current (≈0.1pA) and a low breakdown voltage (8.5V) at room temperature (RT). A low dark count rate (DCR) of 156.8cps/μm² at 3V excess bias is estimated at RT. A peak quantum efficiency (QE) of 96.41% is also measured under a wavelength of 423 nm at 4V. This BSI SPAD indicates a peak photon detection probability (PDP) of 69.51% upon a wavelength of 423 nm at 3V excess bias. A significant expansion of the UV sensitivity down to a wavelength of 291 nm is represented with a PDP of 15.56% at 3V excess bias. To the best of our knowledge, the detection efficiency of this ultrathin BSI SPAD in the UV wavelength regime down to 291 nm is the best result ever reported for Si-based BSI SPAD in spite of the absence of an integrated CMOS circuitry.

Monolithic Single PMUT-on-CMOS Ultrasound System With +17 dB SNR for Imaging Applications

This article presents a fully integrated ultrasound system based on a single piezoelectric micromachined ultrasonic transducer (PMUT) monolithically fabricated with a $0.13~\mu \text{m}$ complementary metal oxide semiconductor (CMOS) process analog front-end circuitry. The PMUT consists of an aluminum nitride, AlN, squared device with $80~\mu \text{m}$ side that resonates at 2.4 MHz in liquid environment. The monolithic integration of the PMUT with the CMOS circuitry allows a reduction of the parasitic capacitance, a reduction of the electronic noise contribution and a clear improvement in the Signal-to Noise ratio (SNR ~ 27 dB better) compared to a non-integrated equivalent system. A pulse-echo experiment with the single PMUT-on-CMOS for transmitting and sensing simultaneously is demonstrated, ensuring a 17.3 dB SNR, higher than the minimal necessary for accurate fingerprint images, paving the way towards a pixel sized imaging system with no need of multiple simultaneous PMUTs transmitters. Consuming only 0.3 mW and getting an input-referred noise of 3.26 mPa/ $\surd $ Hz at 2.4 MHz, the proposed pulse-echo system achieves a competitive noise efficient factor in comparison with the state-of-the-art.

A silicon-based neural probe with densely-packed low-impedance titanium nitride microelectrodes for ultrahigh-resolution in vivo recordings

In this study, we developed and validated a single-shank silicon-based neural probe with 128 closely-packed microelectrodes suitable for high-resolution extracellular recordings. The 8-mm-long, 100-µm-wide and 50-µm-thick implantable shank of the probe fabricated using a 0.13-µm complementary metal-oxide-semiconductor (CMOS) metallization technology contains square-shaped (20 × 20 µm2), low-impedance (~ 50 kΩ at 1 kHz) recording sites made of rough and porous titanium nitride which are arranged in a 32 × 4 dense array with an inter-electrode pitch of 22.5 µm. The electrophysiological performance of the probe was tested in in vivo experiments by implanting it acutely into neocortical areas of anesthetized animals (rats, mice and cats). We recorded local field potentials, single- and multi-unit activity with superior quality from all layers of the neocortex of the three animal models, even after reusing the probe in multiple (> 10) experiments. The low-impedance electrodes monitored spiking activity with high signal-to-noise ratio; the peak-to-peak amplitude of extracellularly recorded action potentials of well-separable neurons ranged from 0.1 mV up to 1.1 mV. The high spatial sampling of neuronal activity made it possible to detect action potentials of the same neuron on multiple, adjacent recording sites, allowing a more reliable single unit isolation and the investigation of the spatiotemporal dynamics of extracellular action potential waveforms in greater detail. Moreover, the probe was developed with the specific goal to use it as a tool for the validation of electrophysiological data recorded with high-channel-count, high-density neural probes comprising integrated CMOS circuitry.

A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit

Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore’s law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + “Molecular”) architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

Integrated nanoplasmonic waveguides for magnetic, nonlinear, and strong-field devices

Abstract As modern complementary-metal-oxide-semiconductor (CMOS) circuitry rapidly approaches fundamental speed and bandwidth limitations, optical platforms have become promising candidates to circumvent these limits and facilitate massive increases in computational power. To compete with high density CMOS circuitry, optical technology within the plasmonic regime is desirable, because of the sub-diffraction limited confinement of electromagnetic energy, large optical bandwidth, and ultrafast processing capabilities. As such, nanoplasmonic waveguides act as nanoscale conduits for optical signals, thereby forming the backbone of such a platform. In recent years, significant research interest has developed to uncover the fundamental physics governing phenomena occurring within nanoplasmonic waveguides, and to implement unique optical devices. In doing so, a wide variety of material properties have been exploited. CMOS-compatible materials facilitate passive plasmonic routing devices for directing the confined radiation. Magnetic materials facilitate time-reversal symmetry breaking, aiding in the development of nonreciprocal isolators or modulators. Additionally, strong confinement and enhancement of electric fields within such waveguides require the use of materials with high nonlinear coefficients to achieve increased nonlinear optical phenomenon in a nanoscale footprint. Furthermore, this enhancement and confinement of the fields facilitate the study of strong-field effects within the solid-state environment of the waveguide. Here, we review current state-of-the-art physics and applications of nanoplasmonic waveguides pertaining to passive, magnetoplasmonic, nonlinear, and strong-field devices. Such components are essential elements in integrated optical circuitry, and each fulfill specific roles in truly developing a chip-scale plasmonic computing architecture.

Pulse-Echo Ultrasound Imaging Using an AlN Piezoelectric Micromachined Ultrasonic Transducer Array With Transmit Beam-Forming

This work demonstrates short-range and high-resolution ultrasonic imaging using 8 MHz aluminum nitride (AlN) piezoelectric micromachined ultrasonic transducer (PMUT) arrays, which are compatible with complementary metal-oxide semiconductor circuitry and wafer-level mass manufacture. Because AlN has a low dielectric constant, the PMUTs have low capacitance and a custom 1.8 V interface application-specified integrated circuit with on-chip charge-pump (1.8 to 32 V) is capable of providing sufficient output current to drive the PMUT array. Transmit beam-forming is used to produce a 90 μm focused acoustic beam-width. A pressure map measured with a needle hydrophone agrees with finite element method-simulations. Finally, 1-D and 2-D pulse-echo imaging was conducted using metal targets.

CMOS MEMS Fabrication Technologies and Devices.

This paper reviews CMOS (complementary metal-oxide-semiconductor) MEMS (micro-electro-mechanical systems) fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator) CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

Modeling and Experimental Demonstration of a Hopfield Network Analog-to-Digital Converter with Hybrid CMOS/Memristor Circuits.

The purpose of this work was to demonstrate the feasibility of building recurrent artificial neural networks with hybrid complementary metal oxide semiconductor (CMOS)/memristor circuits. To do so, we modeled a Hopfield network implementing an analog-to-digital converter (ADC) with up to 8 bits of precision. Major shortcomings affecting the ADC's precision, such as the non-ideal behavior of CMOS circuitry and the specific limitations of memristors, were investigated and an effective solution was proposed, capitalizing on the in-field programmability of memristors. The theoretical work was validated experimentally by demonstrating the successful operation of a 4-bit ADC circuit implemented with discrete Pt/TiO2−x/Pt memristors and CMOS integrated circuit components.

CMOS-Based High-Density Neural Probes with Improved Scheme for Addressing Recording and Stimulation Channels

This paper presents the design, fabrication and characterization of high-density neural probes based on complementary-metal-oxide-semiconductor (CMOS) technology. A new version of the electronic depth control (EDC) addressing scheme is implemented in the slender probe shaft enabling an increased number of simultaneously addressable electrodes compared to our previous EDC devices. Two further channels allow operating selected electrodes for purposes of stimulation or local referencing. Probes with a shaft width of 100 μm and lengths up to 10 mm carrying a maximum number of 334 electrodes with an inter-electrode spacing of 30 μm have been implemented. The integrated CMOS circuitry is realized using the commercial 0.18 μm double-poly, six-metal CMOS process from XFAB, followed by post-CMOS processing of the electrode metallization and probe geometry. The probe functionality is verified by measuring the impedance of single and combined electrodes. Pt and IrOx electrodes are characterized; they reveal impedance values of 2±0.9 MΩ and 162±40 kΩ, respectively, at 1 kHz.

Stress analysis of ultra-thin silicon chip-on-foil electronic assembly under bending

In this paper we investigate the bending-induced uniaxial stress at the top of ultra-thin (thickness μm) single-crystal silicon (Si) chips adhesively attached with the aid of an epoxy glue to soft polymeric substrate through combined theoretical and experimental methods. Stress is first determined analytically and numerically using dedicated models. The theoretical results are validated experimentally through piezoresistive measurements performed on complementary metal-oxide-semiconductor (CMOS) transistors built on specially designed chips, and through micro-Raman spectroscopy investigation. Stress analysis of strained ultra-thin chips with CMOS circuitry is crucial, not only for the accurate evaluation of the piezoresistive behavior of the built-in devices and circuits, but also for reliability and deformability analysis. The results reveal an uneven bending-induced stress distribution at the top of the Si-chip that decreases from the central area towards the chipʼs edges along the bending direction, and increases towards the other edges. Near these edges, stress can reach very high values, facilitating the emergence of cracks causing ultimate chip failure.

Ion traps fabricated in a CMOS foundry

We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

Broadband Millimeter-Wave Propagation Measurements and Models Using Adaptive-Beam Antennas for Outdoor Urban Cellular Communications

The spectrum crunch currently experienced by mobile cellular carriers makes the underutilized millimeter-wave frequency spectrum a sensible choice for next-generation cellular communications, particularly when considering the recent advances in low cost sub-terahertz/millimeter-wave complementary metal-oxide semiconductor circuitry. To date, however, little is known on how to design or deploy practical millimeter-wave cellular systems. In this paper, measurements for outdoor cellular channels at 38 GHz were made in an urban environment with a broadband (800-MHz RF passband bandwidth) sliding correlator channel sounder. Extensive angle of arrival, path loss, and multipath time delay spread measurements were conducted for steerable beam antennas of differing gains and beamwidths for a wide variety of transmitter and receiver locations. Coverage outages and the likelihood of outage with steerable antennas were also measured to determine how random receiver locations with differing antenna gains and link budgets could perform in future cellular systems. This paper provides measurements and models that may be used to design future fifth-generation millimeter-wave cellular networks and gives insight into antenna beam steering algorithms for these systems.

Use of PC mouse components for continuous measuring of human heartbeat

A new technology for remote measuring of vibration sources was recently developed for industrial, medical, and security-related applications [Int. Appl. Patent No: PCT/IL2008/001008]. It requires relatively expensive equipment, such as high-speed complementary metal oxide semiconductor (CMOS) sensors and customized optics. In this paper, we demonstrate how the usage of a simple personal computer (PC) mouse as an optical system composed of a low-power laser and a CMOS circuitry on the same integrated circuit package, can be used to monitor heartbeat from the wrist. The method is based on modifying the mouse optical system in such a way that it will recognize temporal change in skin's vibration profile, generated due to the heart pulses, as mouse movement. The tests that were carried out show a very good correlation between the heartbeat rate measured from human skin and the reference values taken manually.

E-beam invasiveness on 65 nm complementary metal-oxide semiconductor circuitry

Postsilicon debug techniques may require e-beam imaging and nanomachining in the vicinity of live metal-oxide semiconductor (MOS) devices. In that context the authors have investigated the invasiveness of e-beam irradiation on MOS devices to 65 nm integrated circuits, tracked as percent change in ring-oscillator frequencies. Device preparation consisted of backside thinning by mechanical polish, local laser chemical etching to 10 μm Si, and finally, focused ion beam gas-assisted etching, leaving 200–2000 nm remaining Si. This was followed by e-beam exposure at various acceleration energies and doses, from a marginally detectable device degradation dose of 10−4 nC/μm2, and beyond a dose causing total transistor failure around 1.25 nC/μm2, at 30 keV. The authors find that relative frequency degradation depends on irradiation dose as a power law which may be applied to limit unwarranted device degradation. E-beam nanomachining is typically performed at low acceleration energies, conveniently reducing the electron penetration depth, and hence a negligible dose makes it to the devices. This was verified experimentally on 65 nm devices. The results herein put upper bounds on damage-free e-beam-based circuit edit and failure analysis in post-Si debug.

Development and in vivo Demonstration of CMOS-Based Multichip Retinal Stimulator With Simultaneous Multisite Stimulation Capability

A complementary metal-oxide semiconductor (CMOS)-based multichip flexible neural stimulator for retinal prostheses was developed. The multichip retinal stimulator is capable of simultaneous multisite stimulation. An on-chip stimulation generator was implemented on the "unit chip," which is the core device of the multichip retinal stimulator. The performance of the CMOS circuitry was characterized. A new device structure and packaging process was developed. The in vivo retinal stimulation on a rabbit's retina was successfully performed and the multisite stimulation functionality was confirmed.

Hybrid optoelectronic buffer using CMOS memory and optical interfaces for 10-Gbit/s asynchronous variable-length optical packets

A hybrid optoelectronic buffer consisting of a complementary metal-oxide-semiconductor (CMOS) memory and optical/optoelectronic interface devices is described. The interface devices: an all-optical serial-to-parallel converter (SPC), electrical-to-optical parallel-to-serial converter (PSC), and optical clock pulse-train generator (OCPTG) enable write-in/read-out of preamble-free asynchronous high-speed optical packets to/from CMOS memory, and consequently, flexible and highly functional processing of the packets with CMOS circuitry. A prototype hybrid optoelectronic buffer subsystem using a field programmable gate array (FPGA)-based memory and modules for the interface devices is developed and error-free write-in and read-out operation for 10-Gbit/s asynchronous variable-length optical packets is demonstrated.

A memristor-based nonvolatile latch circuit

Memristive devices, which exhibit a dynamical conductance state that depends on theexcitation history, can be used as nonvolatile memory elements by storing information asdifferent conductance states. We describe the implementation of a nonvolatile synchronousflip-flop circuit that uses a nanoscale memristive device as the nonvolatile memory element.Controlled testing of the circuit demonstrated successful state storage and restoration,with an error rate of 0.1%, during 1000 power loss events. These results indicatethat integration of digital logic devices and memristors could open the way fornonvolatile computation with applications in small platforms that rely on intermittentpower sources. This demonstrated feasibility of tight integration of memristorswith CMOS (complementary metal–oxide–semiconductor) circuitry challenges thetraditional memory hierarchy, in which nonvolatile memory is only available as alarge, slow, monolithic block at the bottom of the hierarchy. In contrast, thenonvolatile, memristor-based memory cell can be fast, fine-grained and small, and iscompatible with conventional CMOS electronics. This threatens to upset the traditionalmemory hierarchy, and may open up new architectural possibilities beyond it.

DNA-decorated carbon-nanotube-based chemical sensors on complementary metal oxidesemiconductor circuitry

We present integration of single-stranded DNA (ss-DNA)-decorated single-walled carbonnanotubes (SWNTs) onto complementary metal oxide semiconductor (CMOS) circuitry asnanoscale chemical sensors. SWNTs were assembled onto CMOS circuitry via a low voltagedielectrophoretic (DEP) process. Besides, bare SWNTs are reported to be sensitive tovarious chemicals, and functionalization of SWNTs with biomolecular complexes furtherenhances the sensing specificity and sensitivity. After decorating ss-DNA on SWNTs,we have found that the sensing response of the gas sensor was enhanced (up to ∼ 300% and ∼ 250% for methanol vapor and isopropanol alcohol vapor, respectively) compared with bareSWNTs. The SWNTs coupled with ss-DNA and their integration on CMOS circuitrydemonstrates a step towards realizing ultra-sensitive electronic nose applications.

Effect of radiation therapy on the latest generation of pacemakers and implantable cardioverter defibrillators: A systematic review

The increasing human lifespan and development of technology over the last number of decades has seen an increase in the number of pacemaker and implantable cardioverter defibrillator (ICD) implantations worldwide. Given the number of risk factors common to both heart disease and cancer, it is not uncommon for several of these patients to present for radiation therapy treatment each year. A systematic review was conducted using online databases Medline and Scopus. Results were grouped into in vitro and in vivo studies. In 1994, the American Association of Physicists in Medicine (AAPM) defined guidelines for the management of these patients, which have since been adopted by many radiation oncology departments internationally. More recently, a number of studies have reported an increase in radiation sensitivity of these devices (encompassing the coiled metal leads and generator unit) due to the incorporation of complementary metal oxide semiconductor circuitry. Further avenues of device failure, such as the effect of dose rate and scatter radiation, have only more recently been investigated. There are also the unexplored avenues of electromagnetic interference on devices when incorporating newer treatment technologies such as respiratory gating and intensity modulated radiation therapy. It is suggested that each radiation oncology department employ a policy for the management of patients with ICDs and pacemakers, potentially based upon an updated national or international standard similar to that released by the AAPM in 1994.