Complementary Heterostructure Field Effect Transistor Research Articles

Xs-MET-a reduced complexity fabrication process using complementary heterostructure field effect transistors for analog, low power, space applications

The requirements for space-based integrated circuit applications are defined with an emphasis on being radiation tolerant and low power consuming. Flexible analog signal processors (FASPs) are outlined as a means by which effective circuit designs can be utilized to perform a multitude of tasks. The development of complementary III-V technologies have been proven to meet the demands of the space environment, and have demonstrated the potential for frequency operation beyond 1 GHz using power supply voltages at or below 1.5 Volts. The novel fabrication process known as Xs-MET (pronounced kismet, which uses the Creek letter chi, X, and stands for Complementary Heterostructure Integrated Single Metal Transistor), is introduced as a manufacturing technique to be used in FASP design. The Xs-MET fabrication process is outlined with preliminary device results presented. An example of a FASP circuit design using Xs-MET is provided. Conclusions regarding the utilization of the Xs-MET process for FASPs are outlined with comments focusing on a space-based demonstration.

0.3-μm gate length p-channel AlGaAs/InGaAs heterostructure field effect transistors with high cut-off frequency

P-channel Heterostructure Field Effect Transistors (HFETs) with a 0.3-/spl mu/m gate were fabricated by Mg ion implantation. The maximum transconductance was 68 mS/mm and there was no serious drain or gate leakage current, regardless of this short gate length. The gate turn on voltage (@I/sub gs/=-1 /spl mu/A//spl mu/m) was -2.1 V and its absolute value was large enough for use in complementary HFETs. S-parameters measurements showed a very high cut-off frequency of over 10 GHz. Results indicated the superiority of less-diffusive Mg ion implantation for forming p/sup +/-layer in p-channel HFETs.

DC and noise performance of C-HFET transistors at low drain current densities

The results of measurements of Complementary Heterostructure Field Effect Transistors (C-HFET) are reported. We have investigated the DC, AC and noise parameters of the devices as a function of the operating conditions. In particular, we analysed their behaviour in the low power region at drain current densities less than 2 mA/mm and drain bias voltages less than 2 V. It is shown that the transistors have excellent amplification in this region. We found that the dominant I/ f noise, if measured as an equivalent noise charge on the input gate, is independent of the drain current and the drain bias voltage. Furthermore, the data show that the white serial noise increases with decreasing drain current density and becomes a significant noise source at peaking times less than 25 ns and drain current densities less than 1 mA/mm only. An extrapolation of the measurements shows that the total ENC of a C-HFET input transistor with 25 μm gate-width and 3 μW power dissipation will be about 25 electrons at zero detector capacitance with a slope Δ(ENC)/ΔC det around 440 electrons / pF.

Complementary Hfet Technology for Low-Power Mixed-Mode Applications

AbstractDevelopment of a complementary heterostructure field effect transistor (CHFET) technology for low-power, mixed-mode digital-microwave applications is presented. An earlier digital CHFET technology with independently optimizable transistors which operated with 319 ps loaded gate delays at 8.9 fJ is reviewed. Then work demonstrating the applicability of the digital nJFET device as a low-power microwave transistor in a hybrid microwave amplifier without any modification to the digital process is presented. A narrow band amplifier with a 0.7 × 100 μm nJFET as the active element was designed, constructed, and tested. At 1 mW operating power, the amplifier showed 9.7 dB of gain at 2.15 GHz and a minimum noise figure of 2.5 dB. In addition, next generation CHFET transistors with sub 0.5 μm gate lengths were developed. Cutoff frequencies, ftof 49 GHz and 11.5 GHz were achieved for n- and p-channel FETs with 0.3 and 0.4 μm gates, respectively. These FETs will enable both digital and microwave circuits with enhanced performance.

DC and noise performance of C-HFET transistors at low drain current densities

The results of measurements of complementary heterostructure field effect transistors (C-HFET) are reported. We have investigated the DC, AC and noise parameters of the devices as a function of the operating conditions. In particular, we analysed their behaviour in the low power region at drain current densities less than 2 mA/mm and drain bias voltages less than 2 V. It is shown that the transistors have excellent amplification in this region. We found that the dominant 1/ f noise, if measured as an equivalent noise charge on the input gate, is independent of the drain current and the drain bias voltage. Furthermore, the data show that the white serial noise increases with decreasing drain current density and becomes a significant noise source at peaking times less than 25 ns and drain current densities less than 1 mA/mm only. An extrapolation of the measurements shows that the total ENC of a C-HFET input transistor with 25 μm gate-width and 3 μW power dissipation will be about 25 electrons at zero detector capacitance with a slope Δ(ENC)/ΔC det around 440 electrons /pF.

Evidence of a thermally stable carbon-nitrogen deep level in carbon-doped, nitrogen-implanted, GaAs and AIGaAs

Nitrogen ion implantation is shown to form high resistivity regions (ps ≥ 1 × 1010 Ω/) in C-doped GaAs and Al0.35Ga0.65As that remains compensated after a 900°C anneal. This is in contrast to oxygen or fluorine implantation in C-doped GaAs which both recover the initial conductivity after a sufficiently high temperature anneal (800°C for F and 900°C for O). In C-doped Al0.35Ga0.65As N- and O-implant isolation is thermally stable but F-implanted samples regain the initial conductivity after a 700°C anneal. A dose dependence is observed for the formation of thermally stable N-implant compensation for both the GaAs and AIGaAs samples. A C-N complex is suggested as the source of the compensating defect level for the N-implanted samples. Sheet resistance data vs anneal temperature and estimates of the depth of the defect levels are reported. This result will have application to heterojunction bipolar transistors and complementary heterostructure field effect transistor technologies that employ C-doped AIGaAs or GaAs layers along with high temperature post-implant isolation processing.

Thermally Stable Oxygen and Nitrogen Implant Isolation of C-Doped Al0.35Ga0.65As

ABSTRACTOxygen and nitrogen ion implantation have been applied, for the first time, to C-doped Al0.35Ga0.65As layers produce high resistivity regions (ps ≥ 1×1010 Ω/□) that are stable after annealing at 900 ºC. A dose threshold for stable compensation for both O and N ions was found above 8×1013 cm-2 for samples doped at 2×1018 cm-3. Although O implantation has been reported to form stable compensation in Si-doped and Be-doped AlGaAs, the ability of nitrogen implantation to produce thermally stable compensation has not been previously reported and may be due to a C-N complex. The existence of this C-N complex is supported by results for O- and N-implants into C-doped GaAs where N formed thermally stable compensation but O did not. Sheet resistance data versus anneal temperature and estimates of the depth of the defect levels are reported. This result will have application to heterojunction bipolar transistors and complementary heterostructure field effect transistor technologies that employ C-doped AlGaAs or GaAs layers along with high temperature post-isolation processing.

Gate current in complementary HFETs

Gate current studies have been performed to optimize the performance of HFET (heterostructure field-effect transistor) circuits. Pseudomorphic Al/sub x/Ga/sub 1-x/As/In/sub y/Ga/sub 1-y/As n- and p-channel HFETs with x and y values up to 0.75 and 0.25, respectively, were studied. An analytical theory of the gate current in n- and p-channel HFETs, taking into account both thermionic emission and tunneling is presented.

A complementary heterostructure field effect transistor technology based on InAs/AlSb/GaSb

A complementary heterojunction field effect transistor technology based on the InAs/AlSb/GaSb system is proposed. The structure is formed by the vertical integration of InAs n-channel and GaSb p-channel HFET devices. The superior transport properties of electrons in InAs and holes in GaSb and their band offsets to AlSb or AlSbAs yield devices with transconductances much greater than AlGaAs/GaAs n- and p-channel HFETs. It is shown that a complementary circuit fabricated from these devices could provide room-temperature performance up to six times greater than that predicted for AlGaAs/GaAs complementary circuits. >