Complementary Bipolar Process Research Articles

An ICMR-enhanced three-opamp instrumentation amplifier

The three-operational amplifiers (three-opamp) structure is a widely used topology to design precision instrumentation amplifiers (IAs). However, the input common-mode range (ICMR) of the classical three-opamp IA is limited to the output voltage range of the internal operational amplifiers, resulting in the output voltage range being constrained by the input common-mode voltage. This article proposes an ICMR-enhanced three-opamp topology, which constructs a common-mode feedback (CMFB) loop at the first stage of the IA, enabling the first stage has the capability of common-mode rejection. Hence, the proposed ICMR-enhanced three-opamp IA overcomes the limitation of ICMR, eliminates the constraint of the output voltage range and improves the common-mode rejection ratio (CMRR). The proposed circuit was designed and simulated using complementary bipolar process. The simulation results showed that the output voltage range remains constant regardless of the input common-mode voltages, the CMRR is greater than 150 dB, and the Gain Bandwidth Product (GBW) was 4.1 MHz. The advantages of the proposed ICMR-enhanced three-opamp IA will enable its use in more environments.

Technological and devices modeling of complementary JFETs over a wide temperature range

The article presents the results of process and device modeling results of complementary junction field-effect transistors (JFET). The models necessary for calculating the JFET in the temperature range down to cryogenic were described: the Klaassen model of the carriers mobility (Phillips company model) and Shockley-Read-Hall recombination model, taking into account the doping dependence, Lackner's model of avalanche multiplication, Fermi-Dirac statistics, Slotboom model, designed to describe the dependence of the band gap on the doping concentration. These models take into account the effect of temperature. We have described in detail the model of incomplete ionization of an impurity, which determines the concentration of charge carriers at cryogenic temperatures. The TCAD-based JFET self-heating effect is simulated using a simplified model that significantly reduces the calculation time compared to the thermodynamic model. Studies on the selection of an algorithm for calculating a system of differential equations in the temperature region are carried out. It is shown that the SLIP90 algorithm provides calculations in the entire temperature range down to T = 25 K. The article shows that modification of the design can significantly affect the choice of calculation algorithm. The dependences of the main JFET parameters are analyzed taking into account the selected models on temperature and constructive and technological solutions are proposed to reduce the influence of ultra-low temperatures on the parameters of complementary JFETs.The research results showed that reducing the cut-off voltage reduces the influence of temperature on the shorted-gate drain current JFET in the temperature range. At the same time, n-channel transistors have advantages in terms of a smaller change in parameters over the temperature range down to the temperatures at which the “freezing out” of the impurity charge carriers begins. Several types of transistor topologies were simulated in the temperature range, which showed that the value of the shorted-gate drain current increases linearly with the number of gates. However, there are differences in the dependence of the main parameters in the temperature range depending on the design of the layers of complementary JFETs. Using the emitter region as the top gate weakly affects the parameters of the n-channel JFET in the case of the formation of complementary JFETs in the microwave complementary bipolar technological process, and for the p-channel JFET the temperature stability of the parameters deteriorates. For the p-channel transistor with a gate based on the base region, the temperature stability over the range ΔT = 150–330 K of the shorted-gate drain current is higher than for the transistor with a gate based on the emitter. For the n-channel transistor, the dependence is inverse. Over the range ΔT = 150–77 K, the dependence of the parameters of the transistors for two structures does not differ. In principle, the results show that the change in the ambient temperature has a greater effect on the p-channel transistor than on the n-channel.

CJFET Differential Pairs’ Constructions and Characteristics for Design of Cbicjfet Differential Amplifiers and Differential Difference Amplifiers’

We have developed technology and construction solutions system to increase differential pairs (DP) of JFet with p- and n-channels identity, which are included into silicon complementary bipolar process of SPE “Pulsar” (Moscow). The possibility of creating several types of JFet DPs within the process is shown. The paper presents the results of experimental studies of two types of DP JFet designs with p- and n-channels for the spread of gate-source voltage ΔVGS depending on the drain current and drain-source voltage. The main features of the first design of p-channel JFets were the following: formation of drain/source area due to passive base of npn-transistor and deep collector areas for pnp-transistor; channel formation based on p-layer collector of pnp-transistor; formation of bottom gate using p+ buried layer; top gate formation due to active base and polysilicon emitter of npn-transistor. A feature of the second JFet design was top gate formation due to passive base. The designs of the first and second types of n-channel Jfet were formed similarly, taking into account the replacement of the applied areas of bipolar transistors with opposite ones in the type of conductivity. It was found that with increasing drain current ΔVGS decreases, and with increasing drain-source voltage ΔVGS at high currents increases for DP based on p-channel JFet with the first type of design. The maximum difference ΔVGS was in the range of 5–80 mV for a given differential pair JFet with a p-channel. On plots for DP p-channel JFet with the second type design a significantly lower voltage spread ΔVGS was shown: for example, for the drain current ID = 50 μA the voltage spread ΔVGS did not exceed 10 mV. In this case the voltage spread ΔVGS practially did not depend on drain-source voltage in contrast to differenctial pair of the first type. The second type JFet n-channel differential pairs like for the DP p-channel JFet provided lower spread values in comparison with the first type design: ΔVGS reached values of 5-20 mV. Moreover, for the design of the second type, a significantly weaker effect of the drain-source voltage on ΔVGS was observed at high current densities. The developed designs of differential pairs based on p- and n-channel JFet are recommended for use in organizing the production of CBiCJFet analog circuits, including operations at low temperatures.

CFOA based Integrator Suitable for Analog Signal Processing

Current Feedback Operational Amplifier (AD844) uses a circuit design that emphasizes current-mode operation, which is inherently much faster than voltage-mode operation because it is less effected by stray node-capacitances. When fabricated using high-speed complementary bipolar processes, CFOA’s can be orders of magnitude faster than other available feedback amplifiers ex. VFA’s. With CFOAs, the amplifier gain may be controlled independently of bandwidth. All these constitutes the major advantages of CFOAs. Some new and more efficient active RC integrator circuit realizations, using minimum passive components grounded and a current feedback operational amplifier (CFOA) device are proposed. Integrator with Grounded passive components allow better usability in VLSI. Finally, experimental result by wave processing has been verified using Proteus software.

A complementary bipolar technology family with a Vertically Integrated PNP for high-frequency analog applications

Silicon complementary bipolar processes offer the possibility of realizing high-performance circuits for a variety of analog applications. This paper presents a summary of silicon complementary bipolar process technology reported in recent years. Specifically, an overview of a family of silicon complementary bipolar process technologies, called Vertically Integrated PNP (VIP/sup TMI/) which have been used for the realization of high-frequency analog circuits is presented. Three process technologies, termed VIP-3, VIP-3H, and VIP-4H offer device breakdowns of 40, 85, and 170 V, respectively. These processes feature optimized vertically integrated bipolar junction transistors (PNPs) along with high performance NPN transistors with polycrystalline silicon emitters, low parasitic polycrystalline silicon resistors, and metal-insulator-polycrystalline silicon capacitors. Key issues and aspects of the processes are described. These issues include the polycrystalline silicon emitter optimization and vertical and lateral device isolation in the transistors. Circuit design examples are also described which have been implemented in these technologies.

A 14-bit 100-Msample/s subranging ADC

This paper describes a 14-b analog-to-digital converter designed in a complementary bipolar process. Although it uses a fairly traditional three-stage subranging architecture, several nontraditional techniques are incorporated to achieve 14 bits of performance at a clock rate of 100 MHz. For linearity, the most critical of these is wafer level trimming of the first subrange digital-to-analog converter. Prototype silicon exhibits a spurious-free dynamic range of 90 dB through the Nyquist frequency and a signal-to noise ratio of 74 dB while dissipating 1.25 W.

A monolithic charge-to-amplitude converter (QAC) chip for fast readout of photomultiplier

A fast charge-to-amplitude converter (QAC) chip has been developed for the readout electronics of the electromagnetic calorimeter (ECAL) of the COMPASS experiment at CERN SPS. It is fabricated using a new advanced complementary bipolar process from Harris Semiconductor with intrinsic radiation hardness. The new QAC chip performs the conversion of fast current pulses generated by a photomultiplier tube (PMT) into voltage signals. The output voltage of the QAC is directly proportional to the input current signal. The circuit block diagram, main features and characteristics of the chip are described. Simulation curves as well as test results of QAC prototypes are presented. They show excellent performances for the COMPASS experiment as well as for uses in high energy and nuclear physics experiments to manage fast current signals.

Jitter in ring oscillators

Jitter in ring oscillators is theoretically described, and predictions are experimentally verified. A design procedure is developed in the context of time domain measures of oscillator jitter in a phase-locked loop (PLL). A major contribution is the identification of a design figure of merit /spl kappa/, which is independent of the number of stages in the ring. This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-level jitter performance. The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages. The theoretical predictions are tested on 155 and 622 MHz clock-recovery PLL's which have been fabricated in a dielectrically isolated, complementary bipolar process. The measured closed-loop jitter is within 10% of the design procedure prediction.

Electrostatic aluminum micromirrors using double-pass metallization

The fabrication of aluminum spatial light modulators has so far required costly process engineering efforts. In this paper, a low-cost process approach is presented, suitable for the manufacture of electrostatic micromirror arrays. The mirrors are made from the second metallization of complementary metal oxide semiconductor (CMOS) or bipolar processes deposited in two passes. This metal2 is protected by a photoresist layer that can be patterned using the top passivation mask of the process. No additional layer deposition and layer structuring is necessary during postprocessing. The actuators are released in a simple surface micromachining postprocessing sequence based on a sacrificial aluminum and silicon dioxide etch. Our approach allows one metallization to be used for both the circuitry and the electrooptomechanicaI devices. Deformable mirror arrays of up to 16/spl times/16 pixels were fabricated. Static self-consistent electromechanical simulations using the finite-element method (FEM) toolbox SOLIDIS were performed for a theoretical analysis and optimization of the actuator devices.

A low-power, high-speed, current-feedback op-amp with a novel Class AB high current output stage

A complementary bipolar low-power, high-speed, current-feedback operational amplifier is described. The amplifier incorporates a new Class AB output stage that enables high output current drive of 100 mA and large voltage swing within 1 V of the supply rails while operating at low quiescent current of 1.5 mA. The amplifier was fabricated in a junction-isolated complementary bipolar process with NPN/PNP f/sub t/ of 4.5/3.8 GHz. The amplifier, configured for noninverting gain of two and 100-/spl Omega/ load, provides 3-dB bandwidth of 110 MHz and 2-V pulse rise time of 7 ns.

High tolerance to radiation effects and low noise performance of ACUTE-a complementary bipolar SOI IC technology

The 1/f noise performance of advanced complementary bipolar process from united technologies (ACUTE) is presented as a function of total dose, device geometry, and polarity as well as bias condition during irradiation. ACUTE's noise performance is also compared to noise from devices built on a standard bipolar process. The measured noise spectrum is expressed in terms of Hooge's constant-/spl alpha//sub H/ which normalizes the "noisiness" of the device to its geometry and doping profiles and therefore allows one to compare different structures. The results indicate a significant radiation tolerance and superior low noise of ACUTE process as compared with standard bipolar technology.

A tiny, high-speed, wide-band, voltage-feedback amplifier stable with all capacitive load

A tiny, high-speed, wide-band, voltage-feedback operational amplifier capable of driving unlimited capacitive load is described. A class AB input stage is combined with a modified dynamic Witch-Hazel current mirror to provide high slew rate and wide bandwidth with a small die area and small idle current. An RC network couples part of the capacitive load into the high-impedance node, therefore lowering the dominant pole and increasing stability as a function of capacitive load. The part was fabricated on a 3 GHz, 40 V complementary bipolar process. The quiescent current of the chip is 4.5 mA with 1500 V//spl mu/m slew rate and a -3 dB bandwidth of 235 MHz. The part is operational from /spl plusmn/2.5 V to /spl plusmn/18 V supply range. Die size is 38 mils by 46 mils and it fits into a tiny surface outline transistor (SOT) package.

High Q inductors for wireless applications in a complementary silicon bipolar process

Rectangular spiral inductors with Q's over 12 have been built in a high-speed complementary bipolar process and characterized for use in wireless applications. An accurate broadband model for the inductors has been developed, and a test filter and mixer have been built to verify the performance of the inductors and the accuracy of the model.

Silicon bipolar device structures for digital applications: technology trends and future directions

The double-polysilicon self-aligned bipolar device structure has come a long way since its first inception, but there is still room for further scaling of this structure and continued improvements in performance. An analysis of the current state-of-the-art double-poly structure leads naturally to a discussion of future trends and technologies necessary to continue scaling into the sub-0.25 /spl mu/m regime. In addition, it has become highly desirable to extend bipolar processes in new directions to take advantage of the opportunities offered by emerging materials technologies, such as bonded silicon-on-insulator films and medium or low temperature Si and SiGe epitaxy. Opportunities also exist for high-performance bipolars in BiCMOS technology and in complementary bipolar processes for low-power, high-speed digital applications. These extensions beyond "conventional" bipolar technology will be discussed in terms of their requirements and the device structures that are evolving to match these needs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 7.2 GHz bipolar operational transconductance amplifier for fully integrated OTA-C filters

Using a complementary bipolar junction transistor process having NPN transistors with a maximum short circuit common emitter gain-bandwidth product (ft) of 7.2 GHz and PNP transistors with a maximumft of 4.5 GHz, an operational transconductance amplifier has been designed for a 3-dB bandwidth of 7.2 GHz. The design process invokes new phase compensation strategies and develops innovative new ways of exploiting existing broadbanding techniques. The utility of the design is confirmed by demonstrating its application in two operational transconductance amplifier-capacitance filters. One of these examples is a 225 MHz lowpass filter, while the other is a bandpass filter with a center frequency of 250 MHz.

An analog front-end bipolar-transistor integrated circuit for the SDC silicon tracker

A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker The IC was designed and tested at LBL and was fabricated using AT&T's CBIC-U2, 4 GHz f/sub /spl tau// complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 /spl mu/m pitch double-sided silicon strip detector. The chip measures 6.8 mm/spl times/3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. RMS at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a /spl Phi/=10/sup 14/ protons/cm/sup 2/ have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process. >

High-speed low-power direct-coupled complementary push-pull ECL circuit

This paper presents a high-speed low-power direct-coupled complementary push-pull ECL (DC-PP-ECL) circuit. The circuit features a direct-coupled pnp pull-up and npn pull-down scheme with no extra biasing circuit for the push- and pull-transistor. The bias of the pull-up pnp transistor is established entirely by direct tapping of the existing voltage levels in the current switch. The scheme provides a sharp self-terminating dynamic current pulse through the pull-up pnp transistor during the switching transient, thus completely decoupling the collector load resistor from the delay path. Based on a 0.8-/spl mu/m double-poly self-aligned complementary bipolar process, the circuit offers 2.0X (2.2X) improvement in the loaded delay at 1.0 (0.5) mW/gate and 2.2X improvement in the load driving capability at 1.0 mW/gate compared with the conventional ECL circuit.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Process and device optimization of an analog complementary bipolar IC technology with 5.5-GHz f/sub T/ pnp transistors

An analog complementary bipolar IC process has been developed featuring 9.0-GHz f/sub T/ npn and 5.5-GHz f/sub T/ pnp transistors. Process conditions for emitter, base, and collector of pnp transistors are optimized in order to achieve the best performance tradeoff between current gain, Early voltage, and cutoff frequency. With the optimized process conditions, the H/sub FE//spl times/V/sub A/ of pnp transistors is 350 V with f/sub T/ of 5.5 GHz and f/sub max/ of 8.5 GHz. These high performance pnp transistors have been integrated into an existing 9.0-GHz f/sub T/ npn bipolar process without introducing excessive additional process complexity and manufacturing costs. In addition, Schottky diodes, p-channel junction FET's and laser wafer trimmable precision NiCr resistors have been integrated into the process to enhance analog circuit design capability. >

Circuits to reduce distortion in the diode-bridge track-and-hold

Circuits for reducing distortion in the diode-bridge track-and-hold are described. Adding circuits with current and voltage feedback can reduce distortion caused by the droop and nonlinear junction capacitance of a transistor. A high-speed complementary bipolar process technology is incorporated in the circuit design for its flexibility. SPICE II simulation demonstrates that the circuits reduce distortion in the diode-bridge track-and-hold by 10 to 20 dB. >

Log-domain filtering: an approach to current-mode filtering

A novel approach to filter design, based on Adams' [1] ‘log-domain’ filters, is proposed that yields a truly current-mode circuit realisation. Adams' idea, which was introduced in a limited context, is generalised to permit a complete distortionless synthesis procedure, which results in circuit implementations readily realisable using complementary bipolar processes. It is shown that, by introducing an exponential map on the state-space description of the desired linear system, a log-domain filter can be fully realised with transistors configured in current mirror-type groupings, current sources and capacitors. Owing to the mapping, the state variables are intrinsically related to current, and not voltage, in the resulting circuits, a fact that emphasises the current-mode nature of the design. A general biquadratic filter section is designed, and, following discussion of cascading sections, a seventh-order Chebychev lowpass filter is designed. All designed circuits are shown to be tunable over a two-decade range in frequency while their characteristics are accurately preserved, even for biquad sections whose f0Q product is greater than fT/10. The Chebychev filter is shown in simulation to possess nearly 60 dB dynamic range relative to 0.9% THD, with a cutoff frequency of nearly 5 MHz, using transistor models from AT&T's CBIC-R 300 MHz complementary bipolar process.