Comparator-based Switched-capacitor Research Articles

A low power 10‐bit 1 MS/s cyclic analog to digital converter for complementary metal oxide semiconductors image sensors with comparator‐based switched‐capacitor technique

AbstractThis paper proposes a power‐optimized column‐parallel cyclic analog to digital converter (ADC) for complementary metal oxide semiconductors (CMOS) image sensor readout circuits. The design combines a 2.5‐bit/cycle architecture with a comparator shutdown technique based on the comparator‐based switched‐capacitor (CBSC) circuits, which results in a significant reduction in the operating time of the threshold detection comparator compared with conventional CBSC circuits. This reduction in operating time leads to power savings as the threshold detection comparator can be shut down quickly. The paper also presents a comprehensive analysis of the nonideal factors of CBSC circuits and the coarse and fine conversion allocation scheme. The 10‐bit two‐stage comparator‐based cyclic ADC is designed in a 110 nm 1P4 M CMOS technology. Simulation results show that the effective number of bit (ENOB) is 9.7 bits, with each column consuming 103 W of power. The proposed cyclic ADC has a figure of merit (FOM) of 123 fJ/conv‐step. Compared with conventional structures, the proposed design reduces the power consumption of the ADC by 34.3% while maintaining the same level of performance.

Enhanced comparator‐based switched‐capacitor integrator using current conveyor

AbstractNew schematic for comparator‐based switched‐capacitor (CBSC) integrator is proposed. In comparison with conventional CBSC integrators, the presented circuit helps to reduce significantly the power consumption while improving the signal‐to‐noise ratio (SNR) and the defined figure of merit (FOM). This was obtained by using a second‐generation current conveyor (CCII) in charge scheme. The integrator design is based on the 0.18‐μm CMOS technology with a frequency of 5 MHz; the proposed first‐order CBSC integrator exhibits 22.87 dB as SNR and 60 μW as power dissipation at 1.8‐V supply voltage.

Fully differential implementation of a delta-sigma modulator based on the pseudo-pseudo differential technique

Flicker noise and distortion are the main limitations in biomedical applications, especially for Switched Capacitor implementations, where the flicker noise is folded into the signal band. To remove the flicker noise and increase the linearity, the Pseudo-Pseudo Differential (P2D) technique has been proposed, where a single-ended signal is processed in a differential way. This paper presents the first silicon implementation of a second order Comparator-Based Switched-Capacitor (CBSC) delta-sigma modulator based on a variation of the P2D technique. Experimental results in a standard 180 nm CMOS technology show an improvement of 10 dB in the Peak SNDR, 5 dB in the DR, and 9 dB in the SFDR over its pseudo differential counterpart, which is the preferred differential implementation for CBSC circuits. Moreover, it is achieved with a reduction in the power consumption.

A Design Guide for Comparator-Based Switched-Capacitor Integrator

A Design Guide for Comparator-Based Switched-Capacitor Integrator

A comparator-based cyclic analog-to-digital converter with multi-level input tracking boosted preset voltage

In this paper, we propose a comparator-based switched-capacitor (CBSC) architecture using a multi-level input tracking preset voltage scheme. The CBSC is used to compensate for technology scaling and to reduce the power consumption of a 2.8 MS/s 10-bit cyclic analog-to-digital converter (ADC). A multi-level preset voltage tracks the input voltage in order to improve the conversion rate without consuming additional power. Additionally, a comparator, current sources, and a feedback capacitor are shared to reduce the power and area of this cyclic ADC. Near the Nyquist-rate, a prototype implemented in 0.18 μm CMOS technology has a signal-to-noise and distortion ratio of 53.69 dB and a spurious-free dynamic-range of 62.36 dB, while consuming 0.73 mW of power.

ERRATUM: "AN ENERGY EFFICIENT SECOND-ORDER ΣΔ MODULATOR BASED ON THE POWER AND DELAY OPTIMIZATION OF CBSC IIR FILTER"

In this paper a second-order low distortion Sigma-Delta Modulator (ΣΔM) with utilization of Comparator-Based Switched-Capacitor (CBSC)-based IIR filter, is explored. The advantages of this new structure are justified by the reduction of power and area. For this purpose IIR filter block can be made with single CBSC gain stage that has the same accuracy and performance of second-order filter with two Op-amps. The design of CBSC gain stages is intended to minimize the power consumption, and maximize Modulator performance. As shown in the simulation result, for a 20-KHz signal bandwidth, the modulator achieves a dynamic range of 70.2 dB and a peak signal-to-noise and distortion ratio (SNDR) of 68 dB with an over-sampling ratio of 64. In addition it consumes only 198 μW from a 1.8-V power supply at 2.56 MS/s.

AN ENERGY EFFICIENT SECOND-ORDER ΣΔ MODULATOR BASED ON THE POWER AND DELAY OPTIMIZATION OF CBSC IIR FILTER

In this paper a second-order low distortion Sigma-Delta Modulator (ΣΔM) with utilization of Comparator-Based Switched-Capacitor (CBSC)-based IIR filter, is explored. The advantages of this new structure are justified by the reduction of power and area. For this purpose IIR filter block can be made with single CBSC gain stage that has the same accuracy and performance of second-order filter with two Op-amps. The design of CBSC gain stages is intended to minimize the power consumption, and maximize Modulator performance. As shown in the simulation result, for a 20-KHz signal bandwidth, the modulator achieves a dynamic range of 70.2 dB and a peak signal-to-noise and distortion ratio (SNDR) of 68 dB with an over-sampling ratio of 64. In addition it consumes only 198 μW from a 1.8-V power supply at 2.56 MS/s.

A 5th-order ΣΔ modulator with combination of op-Amp and CBSC circuit for ADSL applications

In this letter, a 5th-Order single-loop low distortion Sigma–Delta Modulator (SDM) is implemented with the combination of the comparator-based switched-capacitor (CBSC)-based and op-amp-based techniques for asymmetric digital subscriber line (ADSL) applications. This structure, which uses integrator (CBSC-based) and IIR filter (op-amp-based) concurrently, has relatively fewer feed-forward paths and modulator coefficients for sensitivity reduction to mismatch. To lower the power consumption of the modulator, the integrators are implemented with CBSC, the IIR filter block is implemented by single OTA, and a passive adder is used to realize the adder at the input of the 5-bit quantizer. The design purpose is minimizing the power consumption while the dynamic performance maintains high. As shown in the simulation result, for a 2-MHz signal bandwidth, the modulator achieves a dynamic range (DR) of 86.5 dB and a peak signal-to-noise and distortion ratio (SNDR) of 85 dB with an oversampling ratio of 8. In addition it consumes 18.75 mW from a 1.8-V power supply at 32 MS/s, which obtains a figure of merit of 1.6e−3.

Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset, and comparator delay compensation

We present a differential comparator-based switched-capacitor (CBSC) pipelined analog-to-digital converter (ADC) with comparator preset, and comparator delay compensation. Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution from 2.5-bit to 7.05-bit. The ADC is manufactured in a 90 nm CMOS technology, with a core area of 0.85 mm × 0.35 mm, a 1.2 V supply for the core and 1.8 V for the input switches. It has an effective number of bits (ENOB) of 7.05-bit, and a power dissipation of 8.5 mW at 60 MS/s.

High-accuracy Comparator-Based Switched-Capacitor structure

This paper analysis the conventional Comparator-Based Switched-Capacitor (CBSC) structure and presents a modified structure that uses interposing middle-phase in charge-transfer mode to solve the tight trade-off between accuracy, speed, and input-swing at no extra power. To meet the accuracy, speed and input-swing requirements, appropriate values of design parameters are analytically discussed and a procedure for choosing optimum values for design is presented. Moreover, digital controller for current sources and comparator are given for the new structure. The effectiveness of the proposed structure is verified through simulation of a gain-stage using a 0.13-um CMOS-technology with 1V power-supply and comparing with conventional CBSC.

A12b, 40-MS/s, 4.1mW fully differential CBSC pipelined ADC in 0.18.MU.m CMOS

In this paper a fully differential comparator-based switched-capacitor (CBSC) pipelined ADC is presented. For better performance and accuracy, we modified the differential architecture and introduced some practical issues on preset levels designing. For comparison, we used a simple comparator which can compensate offset easily. Finally we designed a 12b 40MS/s Fully Differential CBSC Pipelined ADC with proposed architecture in a 0.18-µm standard CMOS process. It achieves 75.2-dB spurious-free-dynamic range (SFDR) and 69.78-dB SNDR. In addition it consumes 4.1mW from a 1.8-V power supply at 40MS/s, which obtains a figure of merit of 460fJ/step.

A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing

A 10-MS/s-to-100-kS/s power-scalable fully differential comparator-based switched-capacitor (CBSC) 10-bit pipelined analog-to-digital converter (ADC) is presented. To operate over a wide range of sampling rates, an adaptive biasing technique is proposed to enhance both linearity and signal-to-noise-plus-distortion ratio (SNDR) at low sampling rates. This ADC has been fabricated in a 0.18-?m standard CMOS process. It achieves 62.3-dB spurious-free-dynamic range (SFDR) and 53.3-dB SNDR while being sampled at 10 MS/s and consuming 1.95 mW from a 1.8-V power supply, which obtains a figure of merit of 510 fJ/step. With the utilization of adaptive biasing, the SNDR increases from 53.3 to 56.4 dB at most when decreasing the sampling rate. In addition, its power consumption continuously reduces from 1.95 mW (10 MS/s) to 158.4 ?W (100 kS/s).

A10b, 20-MS/s, 2.6mW fully differential CBSC pipelined ADC in 0.18.MU.m CMOS

In this paper a new structure for comparator-based switched-capacitor circuits has been presented. In contrast with the conventional architecture the proposed algorithm utilizes an extra comparator to make a variable comparator threshold, in order to attenuating the overshoot at the end of the coarse phase. for better designing we introduced some practical issues on preset levels designing. After that this paper proposes a feed forward offset compensation which can avoid offset accumulation in proposed architectures. Finally we designed a 10b 20MS/s Fully Differential CBSC Pipelined ADC with proposed architecture in a 0.18-µm standard CMOS process. It achieves 74.4-dB spurious-free-dynamic range (SFDR) and 58.34-dB SNDR. In addition It consumes 2.6mW from a 1.8-V power supply at 40MS/s, which obtains a figure of merit of 210fJ/step.

Analysis of Errors in a Comparator-Based Switched-Capacitor Biquad Filter

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Comparator-based switched-capacitor (CBSC) techniques have become popular in reducing power consumption and increasing the speed of data converters. This brief investigates the use of CBSC techniques for implementing a biquad filter. A CBSC implementation of a low-pass biquad is proposed, and the sources of error are analyzed. It is shown that implementing the lossy integrator as the last stage produces a lower offset voltage. The sensitivity of the biquad <formula formulatype="inline"><tex Notation="TeX">$\omega_{0}$</tex></formula> and <formula formulatype="inline"><tex Notation="TeX"> $Q$</tex></formula> to the CBSC overshoot error is shown to be similar to that of the finite operational amplifier gain error in a switched-capacitor filter. Simulation results confirm the presented theory. </para>

A Fully Differential Comparator-Based Switched-Capacitor $\Delta\Sigma$ Modulator

In this brief, a fully differential comparator-based switched-capacitor (CBSC) second-order delta-sigma (DeltaSigma) modulator is presented. To ensure differential operation, the CBSC DeltaSigma modulator utilizes a common-mode feedback circuit to balance the pull-up current and the pull-down current in the ramp generator. This modulator has been fabricated in a standard 0.18-mum CMOS process. The active area is 0.21 mm2, and the power consumption, excluding output buffers, is 0.42 mW from a 1.8-V supply. This modulator achieves 65.3-dB signal-to-noise-plus-distortion ratio and an input dynamic range of 71 dB when sampled at 2.56 MS/s (OSR = 64).

Noise Analysis for Comparator-Based Circuits

Noise analysis for comparator-based circuits is presented. The goal is to gain insight into the different sources of noise in these circuits for design purposes. After the general analysis techniques are established, they are applied to different noise sources in the comparator-based switched-capacitor pipeline analog-to-digital converter (ADC). The results show that the noise from the virtual ground threshold detection comparator dominates the overall ADC noise performance. The noise from the charging current can also be significant, depending on the size of the capacitors used, but the contribution was small in the prototype. The other noise sources have contributions comparable to those in op-amp-based designs, and their effects can be managed through appropriate design. In the prototype, folded flicker noise was found to be a significant contributor to the broadband noise because the flicker noise of the comparator extends beyond the Nyquist rate of the converter.

A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC

Zero-crossing-based circuits (ZCBC) are introduced as a generalization of comparator-based switched-capacitor circuits (CBSC). To demonstrate this concept, an 8-bit, 200 MS/s, pipelined ADC is implemented in a 0.18 CMOS technology. A dynamic zero-crossing detector and current source replace the functionality of an opamp to realize a precision charge transfer. Furthermore, current source splitting improves linearity at high speeds and bit decision flip-flops replace traditional bit decision comparators for increased speed. The complete ADC draws no static current and consumes 8.5 mW of power. The corresponding FOM is 0.38 pJ/step at 100 MS/s and 0.51 pJ/step at 200 MS/s.

Cascade delta-sigma modulator with pseudo-differential comparator-based switched-capacitor gain stage

A low-power, multi-stage delta-sigma modulator with comparator-based switched-capacitor (CBSC) gain stages is presented. The presented design eliminates the need for operational amplifiers and replaces them by comparators with current sources at their outputs to alleviate the effects of continued technology scaling on analog and mixed-signal circuits. The proposed technique significantly reduces power consumption and can be applied to switched-capacitor delta-sigma modulators of arbitrary order. Based on the proposed methodology, a 2-1 cascade, single-bit, pseudo-differential switched-capacitor delta-sigma modulator is developed and achieves a SNDR of 76.8 dB with an oversampling ratio of 64 at a clock frequency of 8 MHz.

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves replacing the operational amplifier in a standard switched-capacitor circuit with a comparator and a current source. During charge transfer, the comparator detects the virtual ground condition in place of the opamp which normally forces the virtual ground condition. A prototype 1.5-bit/stage 10-bit 7.9-MS/s pipeline ADC was designed using the comparator-based switched-capacitor technique. The prototype ADC was implemented in 0.18-mum CMOS. It achieves an ENOB of 8.6 bits for a 3.8-MHz input signal and dissipates 2.5 mW