Compact VLSI Implementation Research Articles

A new neuron and synapse model suitable for low power VLSI implementation

A new dynamical neuron model for low power and compact VLSI implementation is presented. The model is capable of generating the most common type of spiking patterns. Judicious use of subthreshold CMOS design techniques leads to a very effective low-power CMOS Neuron and synapse circuits. The circuit consists of a single first-order log domain filter and a few hyperbolic function generators. We have also developed a circuit which realizes the synaptic interconnections of the neurons. Based on this complete neuron and synapse model, we studied synchronization behavior of two reciprocally interconnected neurons with excitatory and inhibitory couplings. Owing to the use of log-domain design and current-mode design, the circuits occupying low chip area and having very low power consumption are obtained even at real biological time-scale operation. These features make these circuits especially suitable for hybrid interface applications and large scale VLSI neuromorphic networks.

Delay-Power Performance of High Speed Radix 32 Booth Multiplier in 40nm Process Technology

Multipliers play an important role in today’s digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets – high speed, low power consumption, regularity of layout and hence less area or even combination of them in one multiplier thus making them suitable for various high speed, low power and compact VLSI implementation This thesis looks into the design and simulations of 32 bit booth multiplier with high speed carry select adder in 40 nm process technology and effect of temperature on power consumption. Process level simulation has been carried out on Xilinx suite 12.3.1 and Model -sim. For Investigation about Power, X Power Analyser is used which shows variation of power with respect to temperature.

Fast pipelined complex convolver

A fast architecture for fully-pipelined convolution of complex numbers is presented. High regularity and modularity allow for a compact VLSI implementation. High throughput efficiently supports massive computation.

Design of HDTV subband filterbanks considering VLSI implementation constraints

The design of a subband filter bank for encoding high-definition television (HDTV) signals at 140 Mb/s is presented. Considering filter reconstruction errors, quantization errors, signal statistics, and VLSI implementation constraints in the filter design, quadrature mirror filters (QMFs) are found to be most appropriate. As a result, two-dimensional QMFs with 10 coefficients for vertical and 14 coefficients for horizontal filtering are proposed. A compact VLSI implementation is possible by filter architectures utilizing the special features of QMFs. The timing constraints can be relaxed by the use of polyphase filter structures for decimation and interpolation. Utilization of the symmetry property of QMFs reduces the arithmetic hardware expense approximately by a factor of two. By taking advantage of the special VLSI architecture and optimization of the circuit technique, a one-chip realization for each, the analysis and synthesis filter bank of the luminance components can be achieved in a 1- mu m CMOS technology. A second pair of filter-bank chips is required for the two chrominance components.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

CORDIC-based HiFi digital FM demodulator algorithm for compact VLSI implementation

A robust HiFi digital FM demodulation algorithm is discussed. Simulations demonstrate a performance surpassing analogue top-class receivers: a signal/noise ratio better than 90 dB for a sufficiently large carrier/noise ratio and a distortion level below 0.1% at 1 kHz modulation. For compact VLSI implementation, efficient shift-and-add-based CORDIC and IIR filter algorithms are used.