Compact Hardware Implementation Research Articles

Breaking Ground: A New Area Record for Low-Latency First-Order Masked SHA-3

SHA-3, the latest hash standard from NIST, is utilized by numerous cryptographic algorithms to handle sensitive information. Consequently, SHA-3 has become a prime target for side-channel attacks, with numerous studies demonstrating successful breaches in unprotected implementations. Masking, a countermeasure capable of providing theoretical security, has been explored in various studies to protect SHA-3. However, masking for hardware implementations may significantly increase area costs and introduce additional delays, substantially impacting the speed and area of higher-level algorithms. In particular, current low-latency first-order masked SHA-3 hardware implementations require more than four times the area of unprotected implementations. To date, the specific structure of SHA-3 has not been thoroughly analyzed for exploitation in the context of masking design, leading to difficulties in minimizing the associated area costs using existing methods. We bridge this gap by conducting detailed leakage path and data dependency analyses on two-share masked SHA-3 implementations. Based on these analyses, we propose a compact and low-latency first-order SHA-3 masked hardware implementation, requiring only three times the area of unprotected implementations and almost no fresh random number demand. We also present a complete theoretical security proof for the proposed implementation in the glitch+register-transition-robust probing model. Additionally, we conduct leakage detection experiments using PROLEAD, TVLA and VerMI to complement the theoretical evidence. Compared to state-of-theart designs, our implementation achieves a 28% reduction in area consumption. Our design can be integrated into first-order implementations of higher-level cryptographic algorithms, contributing to a reduction in overall area costs.

A Compact Hardware Design and Implementation on FPGA Based Hybrid of AES and Keccak SHA3-512 for Enhancing Data Security

Data security means protecting important information from unauthorised persons. In a security system, cryptography is the most secure method. Cryptography has many kinds, but the Advanced Encryption Standard (AES) is the most secure system. If combined with AES and Secure Hash Algorithm-3-512Bits (SHA3-512), it becomes compact, more secure, and more authenticated for data communications. The proposed methodology is a hybrid cryptography technique that combines AES with the SHA3-512 algorithm. This system becomes a strong, secure system and produces a strong cipher text. The proposed method AES/SHA3-512 is Hardware implementation on the Artix-7 FPGA family yields the lowest cost and highest hardware efficiency with a reduction in area usage of LUT 18.49%, Flip Flops 0.83%, and IO 3.8%. The proposed architecture is synthesised and simulated using the Vivado 2017.2 version Tool.

Coupled Ferroelectric-Photonic Memory in a Retinomorphic Hardware for In-Sensor Computing.

The development of all-in-one devices for artificial visual systems offers an attractive solution in terms of energy efficiency and real-time processing speed. In recent years, the proliferation of smart sensors in the growth of Internet-of-Things (IoT) has led to the increasing importance of in-sensor computing technology, which places computational power at the edge of the data-flow architecture. In this study, a prototype visual sensor inspired by the human retina is proposed, which integrates ferroelectricity and photosensitivity in two-dimensional (2D) α-In2Se3 material. This device mimics the functions of photoreceptors and amacrine cells in the retina, performing optical reception and memory computation functions through the use of electrical switching polarization in the channel. The gate-tunable linearity of excitatory and inhibitory functions in photon-induced short-term plasticity enables to encode and classify 12000 images in the Mixed National Institute of Standards and Technology (MNIST) dataset with remarkable accuracy, achieving ≈94%. Additionally, in-sensor convolution image processing through a network of phototransistors, with five convolutional kernels electrically pre-programmed into the transistors is demonstrated. The convoluted photocurrent matrices undergo straightforward arithmetic calculations to produce edge and feature-enhanced scenarios. The findings demonstrate the potential of ferroelectric α-In2Se3 for highly compact and efficient retinomorphic hardware implementation, regardless of ambipolar transport in the channel.

An Extended Spatiotemporal Contextual Learning and Memory Network Model for Hardware Implementation

A spatiotemporal contextual learning and memory network (STCLMN) model was proposed based on the hippocampal CA1 network using the difference equations suitable for digital computer simulations. However, the inherent capability of handling and processing of continuous-time asynchronous signals (spikes) cannot be fully employed in the STCLMN model. Furthermore, digital circuit implementation of the STCLMN is not suitable for real-time edge applications, wherein small size, low power consumption, and real-time learning capability are necessary. Therefore, this study extends the original STCLMN model using a set of differential equations to overcome the above problems encountered by STCLMN for asynchronous circuit implementation. The minimum accuracy required for a compact and low-power hardware implementation of the proposed model is then investigated. The validity and feasibility of the proposed model are confirmed through numerical simulations and experiments with a small mixed analog/digital circuit based on the investigated accuracy. In this study, LIF neurons are used because of their ease of circuit implementation. The proposed eSTCLMN model would enable an efficient circuit implementation of an asynchronous spiking neural network with spatiotemporal contextual one-shot learning and memory.

ReAdapt: A Reconfigurable Datapath for Runtime Energy-Quality Scalable Adaptive Filters

This paper proposes ReAdapt–a reconfigurable datapath architecture for scaling the energy-quality trade-off of adaptive filtering at runtime. The ReAdapt can dynamically select four adaptive filtering algorithms for gradating complexity levels during runtime by reconfiguring the processing flow in its datapath and by blocking the switching activity (e.g., reducing the CMOS dynamic power) of unused modules with data-gating. The ReAdapt proposal can scale the energy-quality trade-off by choosing the following four different levels of filter algorithms complexity: 1) least mean square (LMS); 2) partial update normalized LMS (PU-NLMS); 3) set-membership normalized LMS (SM-NLMS); 4) normalized LMS (NLMS). The ReAdapt architecture reuses common modules of each adaptive filter, resulting in a compact VLSI hardware implementation. The ReAdapt architecture operation is implemented in a case-study for interference mitigation for electroencephalogram (EEG) signal processing. The hardware synthesis results show an increase of 6.80 times in throughput and at least a reduction of 2.84 times in energy per operation compared with the state-of-the-art adaptive filters. This paper also investigates the benefits of dynamically reconfiguring the four ReAdapt operating modes at runtime for different levels of signal-to-noise ratio (SNR) for the processed signals. We also demonstrate that dynamically reconfiguring the ReAdapt operating modes during runtime results in an optimal energy-quality trade-off which is advantageous over the conventional single static mode.

TripleBrain: A Compact Neuromorphic Hardware Core With Fast On-Chip Self-Organizing and Reinforcement Spike-Timing Dependent Plasticity.

Human brain cortex acts as a rich inspiration source for constructing efficient artificial cognitive systems. In this paper, we investigate to incorporate multiple brain-inspired computing paradigms for compact, fast and high-accuracy neuromorphic hardware implementation. We propose the TripleBrain hardware core that tightly combines three common brain-inspired factors: the spike-based processing and plasticity, the self-organizing map (SOM) mechanism and the reinforcement learning scheme, to improve object recognition accuracy and processing throughput, while keeping low resource costs. The proposed hardware core is fully event-driven to mitigate unnecessary operations, and enables various on-chip learning rules (including the proposed SOM-STDP & R-STDP rule and the R-SOM-STDP rule regarded as the two variants of our TripleBrain learning rule) with different accuracy-latency tradeoffs to satisfy user requirements. An FPGA prototype of the neuromorphic core was implemented and elaborately tested. It realized high-speed learning (1349 frame/s) and inference (2698 frame/s), and obtained comparably high recognition accuracies of 95.10%, 80.89%, 100%, 94.94%, 82.32%, 100% and 97.93% on the MNIST, ETH-80, ORL-10, Yale-10, N-MNIST, Poker-DVS and Posture-DVS datasets, respectively, while only consuming 4146 (7.59%) slices, 32 (3.56%) DSPs and 131 (24.04%) Block RAMs on a Xilinx Zynq-7045 FPGA chip. Our neuromorphic core is very attractive for real-time resource-limited edge intelligent systems.

Automatic Search of Rectangle Attacks on Feistel Ciphers: Application to WARP

In this paper we present a boomerang analysis of WARP, a recently proposed Generalized Feistel Network with extremely compact hardware implementations. We start by looking for boomerang characteristics that directly take into account the boomerang switch effects by showing how to adapt Delaune et al. automated tool to the case of Feistel ciphers, and discuss several improvements to keep the execution time reasonable. This technique returns a 23-round distinguisher of probability 2−124, which becomes the best distinguisher presented on WARP so far. We then look for an attack by adding the key recovery phase to our model and we obtain a 26-round rectangle attack with time and data complexities of 2115.9 and 2120.6 respectively, again resulting in the best result presented so far. Incidentally, our analysis discloses how an attacker can take advantage of the position of the key addition (put after the S-box application to avoid complementation properties), which in our case offers an improvement of a factor of 275 of the time complexity in comparison to a variant with the key addition positioned before. Note that our findings do not threaten the security of the cipher which iterates 41 rounds.

Highly-accurate binary tiny neural network for low-power human activity recognition

An ultra low power hardware implementation of Human Activity Recognition systems imposes very tight constraints. Therefore it requires a very thoughtful balancing between highly accurate results and the reduction of the allocated physical resources. Deep Learning models provide the highest accuracies, however their typical computational complexity and memory requirements are not easily deployable in handheld or wearable devices which embody very constrained memory and computation capabilities. In this work, we introduce a new HAR system built with a new Hybrid Binarized Neural Network suitable for a very compact and ultra low-power hardware implementation. The system receives data from MEMS based inertial sensors and makes the acquisitions independent from the sensor spatial orientation and the gravity acceleration signal. The system has been trained and validated on the PAMAP2 and SHL dataset. In both cases, it achieves accuracies higher than 99% in the best case, with different input sensor configurations. A custom circuit has been implemented, which extensively shares circuitry between the different functional sub-modules of the system to minimize the amount of mapped physical resources. The FPGA implementation on a Xilinx Artix 7 achieves a total power dissipation of 72 mW and occupies 6788 LUTs.

Single Image Haze Removal from Image Enhancement Perspective for Real-Time Vision-Based Systems.

Vision-based systems operating outdoors are significantly affected by weather conditions, notably those related to atmospheric turbidity. Accordingly, haze removal algorithms, actively being researched over the last decade, have come into use as a pre-processing step. Although numerous approaches have existed previously, an efficient method coupled with fast implementation is still in great demand. This paper proposes a single image haze removal algorithm with a corresponding hardware implementation for facilitating real-time processing. Contrary to methods that invert the physical model describing the formation of hazy images, the proposed approach mainly exploits computationally efficient image processing techniques such as detail enhancement, multiple-exposure image fusion, and adaptive tone remapping. Therefore, it possesses low computational complexity while achieving good performance compared to other state-of-the-art methods. Moreover, the low computational cost also brings about a compact hardware implementation capable of handling high-quality videos at an acceptable rate, that is, greater than 25 frames per second, as verified with a Field Programmable Gate Array chip. The software source code and datasets are available online for public use.

A 4K-Capable FPGA Implementation of Single Image Haze Removal Using Hazy Particle Maps

This paper presents a fast and compact hardware implementation using an efficient haze removal algorithm. The algorithm employs a modified hybrid median filter to estimate the hazy particle map, which is subsequently subtracted from the hazy image to recover the haze-free image. Adaptive tone remapping is also used to improve the narrow dynamic range due to haze removal. The computation error of the proposed hardware architecture is minimized compared with the floating-point algorithm. To ensure real-time hardware operation, the proposed architecture utilizes the modified hybrid median filter using the well-known Batcher’s parallel sort. Hardware verification confirmed that high-resolution video standards were processed in real time for haze removal.

Correlation power analysis and effective defense approach on light encryption device block cipher

AbstractRecently many works have shown that one of the weaknesses of cryptographic algorithms is power analysis attacks on its hardware implementation. This side channel analysis (SCA) is of interest because such attack can leak information of cryptographic algorithms. So, developing attack resistant mechanism is important for hardware security modules. This paper investigates the vulnerability of light encryption device (LED) block cipher, against correlation power analysis. LED is a lightweight block cipher targeted for compact hardware implementation to protect ubiquitous computing data. We use Chipwhisperer capture hardware to capture power traces during encryption of randomly generated plain texts using the same secret key. Our proposed attack successfully retrieves all 64 bits of secret key correctly using only 300 power traces and 256 key guesses. Furthermore, we propose a simple but effective mitigation technique to prevent such attacks.

Hardware Constructions for Error Detection of Number-Theoretic Transform Utilized in Secure Cryptographic Architectures

Polynomial multiplication is one of the most rigorous arithmetic construction of postquantum cryptosystems. Utilizing number-theoretic transformations, the product of such multiplication can be efficiently computed in quasi-linear time $O(n.lgn)$ . Error detection schemes of number-theoretic transform (NTT) architectures are essential to ensure correct mathematical operations, improved security, and thwart active side-channel attacks mounted through faults. NTT is not only significant to post-quantum cryptosystems, but the structure is also valuable to the already existing security protocols, e.g., signature schemes, hash functions, and the like. This paper, for the first time, introduces new error detection schemes of NTT architectures, successfully detecting both permanent and transient faults. Our schemes are based on recomputing with negated, scaled, and swapped operands. We have implemented the proposed schemes on the application-specific integrated circuit (ASIC). Performance and implementation metrics on this hardware platform show acceptable hardware overhead. As our schemes provide acceptable complexity and high efficiency, they can be utilized in compact hardware implementations of constrained applications, e.g., deeply embedded architectures.

Efficient parallel implementation of reservoir computing systems

Reservoir computing (RC) is a powerful machine learning methodology well suited for time-series processing. The hardware implementation of RC systems (HRC) may extend the utility of this neural approach to solve real-life problems for which software solutions are not satisfactory. Nevertheless, the implementation of massive parallel-connected reservoir networks is costly in terms of circuit area and power, mainly due to the requirement of implementing synapse multipliers that increase gate count to prohibitive values. Most HRC systems present in the literature solve this area problem by sequencializing the processes, thus loosing the expected fault-tolerance and low latency of fully parallel-connected HRCs. Therefore, the development of new methodologies to implement fully parallel HRC systems is of high interest to many computational intelligence applications requiring quick responses. In this article, we propose a compact hardware implementation for Echo-State Networks (an specific type of reservoir) that reduces the area cost by simplifying the synapses and using linear piece-wise activation functions for neurons. The proposed design is synthesized in a Field-Programmable Gate Array and evaluated for different time-series prediction tasks. Without compromising the overall accuracy, the proposed approach achieves a significant saving in terms of power and hardware when compared with recently published implementations. This technique pave the way for the low-power implementation of fully parallel reservoir networks containing thousands of neurons in a single integrated circuit.

Spike-timing-dependent plasticity learning of coincidence detection with passively integrated memristive circuits

Spiking neural networks, the most realistic artificial representation of biological nervous systems, are promising due to their inherent local training rules that enable low-overhead online learning, and energy-efficient information encoding. Their downside is more demanding functionality of the artificial synapses, notably including spike-timing-dependent plasticity, which makes their compact efficient hardware implementation challenging with conventional device technologies. Recent work showed that memristors are excellent candidates for artificial synapses, although reports of even simple neuromorphic systems are still very rare. In this study, we experimentally demonstrate coincidence detection using a spiking neural network, implemented with passively integrated metal-oxide memristive synapses connected to an analogue leaky-integrate-and-fire silicon neuron. By employing spike-timing-dependent plasticity learning, the network is able to robustly detect the coincidence by selectively increasing the synaptic efficacies corresponding to the synchronized inputs. Not surprisingly, our results indicate that device-to-device variation is the main challenge towards realization of more complex spiking networks.

Preface to the Special Issue on Data Center Communications

Data Center networking requirements have evolved rapidly in recent years. Driven by services that include the Internet of Things, Big Data processing, Cloud Services and Social Media, large-scale Data Center providers are in urgent need to develop scalable solutions that will accommodate the ever growing capacity demands in a cost- and energy-efficient manner and provide simplified data center management and automation. As a result, we have recently seen several important developments in the implementation of interconnects offering ever broader bandwidths, which have attracted fevered discussions on what may be the most effective route forward towards their adoption. Advances in silicon technology have allowed for more compact and affordable hardware implementations. However, the limits to the capabilities of current transceiver and switching technologies are already in sight, forcing Data Center providers to upgrade their hardware every few years. The wide adoption of pluggable 100 Gb/s systems and the technology push towards small form-factor transceivers with capacities that are several multiples of this, triggers the development of a whole new technological ecosystem, including new fibre and device technologies as well as networking concepts and architectures. In this rapidly evolving environment, this Special Issue offers a timely insight to some of the latest research developments in areas including: – Integrated photonic technologies, including sources, switches, silicon photonic integrated circuits and their packaging – Novel fibres to serve Data Center Interconnects – Data Center Communication links – Advanced Data Center networking concepts We hope that this collection of invited papers from some of the leading research groups working on Data Center Communications will provide the readers with a detailed appreciation of the state-of-the-art in this hot application area of optical communications, and that it will inspire further cutting-edge research in the field. We would like to thank all of the authors, as well as the anonymous reviewers of the papers for their hard work towards ensuring a high quality Special Issue. This Issue would not have been realised without the initiative, guidance and patience of Editor-in-Chief Bertrand Desthieux, whose leadership and contribution we gratefully appreciate.

Compact Hardware Implementations of MISTY1 Block Cipher

This paper proposes compact hardware implementations of 64-bit NESSIE proposed MISTY1 block cipher for area constrained and low power ASIC applications. The architectures comprise only one round MISTY1 block cipher algorithm having optimized FO/FI function by re-utilizing S9/S7 substitution functions. A focus is also made on efficient logic implementations of S9 and S7 substitution functions using common sub-expression elimination (CSE) and parallel AND/XOR gates hierarchy. The proposed architecture 1 generates extended key with independent FI function and is suitable for MISTY1 8-rounds implementation. On the other hand, the proposed architecture 2 uses a single FO/FI function for both MISTY1 round function as well as extended key generation and can be employed for MISTY1 [Formula: see text] rounds. To analyze the performance and covered area for ASICs, Synopsys Design Complier, SMIC 0.18[Formula: see text][Formula: see text]m @ 1.8[Formula: see text]V is used. The hardware constituted 3041 and 2331 NAND gates achieving throughput of 171 and 166 Mbps for 8 rounds implementation of architectures 1 and 2, respectively. Comprehensive analysis of proposed designs is covered in this paper.

Design and Implementation of a Digital Secure Code-Shifted Reference UWB Transmitter and Receiver

This paper presents the first compact hardware implementation of a digital code-shifted reference (CSR) ultra-wideband (UWB) transceiver. The security of the transmission is based on changing the physical properties of the transmission without the use of higher level security options. The software models of the designed transceiver are simulated and verified in both floating-point and fixed-point numerical representations. The synthesizable Verilog description of the transceiver architecture is simulated and verified against its fixed-point simulation model. The secure transceiver is implemented on our custom-developed field-programmable gate array (FPGA) board. The characteristic and implementation results of the secure transceiver architecture on the FPGA are presented. The bit error rate performance of the transceiver is measured in real time on the FPGA using an accurate on-chip Gaussian noise generator and is compared with that of the software simulation model. An ASIC architecture of the CSR-UWB transceiver is estimated to occupy 0.019 mm2 and dissipate 0.63 mW from a 1.0 V supply while operating at 82 MHz in a standard 32-nm CMOS technology.

Hardware architecture for large parallel array of Random Feature Extractors applied to image recognition

We demonstrate the use of a low-power and compact hardware implementation of Random Feature Extractor (RFE) core in image recognition applications. We show that weight distributions with zero mean are necessary for good performance in this application. We also show the performance in this application of a recently proposed weight reuse technique that virtually expands the number of random features available from RFE core. Further, we propose a method of reducing computation cost by pruning “incognizant” or redundant random feature neurons. For proof of concept, we validated our approach by using our RFE core as the first stage of Extreme Learning Machine (ELM) – a two layer neural network – and using 12, 800 hidden neurons were able to achieve upto 97.8% accuracy on MNIST database of handwritten digits. The RFE ASIC occupies 5 mm × 5 mm area in 0.35 µm CMOS process. By using the proposed pruning method, an accuracy of 97% is obtained by using only 4749 effective hidden neurons and consuming 6.1 µJ/classify. Input pre-processing and ELM second stage requiring just addition operations can be implemented using digital adders with estimated power consumption of 24.9 nJ/classify. With a total energy consumption of only 6.12 µJ/classify, this low-power mixed signal ASIC can act as a co-processor in portable electronic gadgets with cameras.

VLSI Extreme Learning Machine: A Design Space Exploration

In this paper, we describe a compact low-power high-performance hardware implementation of extreme learning machine for machine learning applications. Mismatches in current mirrors are used to perform the vector-matrix multiplication that forms the first stage of this classifier and is the most computationally intensive. Both regression and classification (on UCI data sets) are demonstrated and a design space tradeoff between speed, power, and accuracy is explored. Our results indicate that for a wide set of problems, $\sigma V_{T}$ in the range of 15–25 mV gives optimal results. An input weight matrix rotation method to extend the input dimension and hidden layer size beyond the physical limits imposed by the chip is also described. This allows us to overcome a major limit imposed on most hardware machine learners. The chip is implemented in a 0.35- $\mu \text{m}$ CMOS process and occupies a die area of around 5 mm $\times 5$ mm. Operating from a 1 V power supply, it achieves an energy efficiency of 0.47 pJ/MAC at a classification rate of 31.6 kHz.

A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding

A High-Throughput and Compact Hardware Implementation for the Reconstruction Loop in HEVC Intra Encoding