Compact Field Programmable Gate Array Research Articles

Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machines.

Field programmable gate array (FPGA) is widely used in the acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the trade-off between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. Here, we propose a ferroelectric field-effect transistor (FeFET)-based context-switching FPGA supporting dynamic reconfiguration to break this trade-off, enabling loading of arbitrary configuration without interrupting the active configuration execution. Leveraging the intrinsic structure and nonvolatility of FeFETs, compact FPGA primitives are proposed and experimentally verified. The evaluation results show our design shows a 63.0%/74.7% reduction in a look-up table (LUT)/connection block (CB) area and 82.7%/53.6% reduction in CB/switch box power consumption with a minimal penalty in the critical path delay (9.6%). Besides, our design yields significant time savings by 78.7 and 20.3% on average for context-switching and dynamic reconfiguration applications, respectively.

A compact and efficient AES-32GF for encryption in small IoT devices

The phenomenal growth of resource constrained devices in IoT set ups has motivated the researchers to develop solutions for securing information flow. In this paper, we present a compact and efficient field programmable gate array (FPGA) implementation of AES with 32-bit data-path named, AES-32GF. The implementation is carried out on different Xilinx FPGAs. In FPGAs, utilization of slices and look up tables (LUTs) reflect on the compactness of the design. Numerical results show that lesser resources are required with smaller data path in comparison with the original standard. With the help of data path compression and Galois field implementation of the s-box resource consumption is minimized. S-box is the most resource consuming component in the AES structure. In our implementation, Artix-7 series FPGA for the same. It results in significant resource savings. In comparison to unrolled AES-128 architecture, it achieves 87 % resource savings. With 595 slices and 2.004 Gbps throughput, AES-32GF cipher achieves an efficiency of 3.37 Mbps/slice. It outperforms other designs in terms of efficiency.•A compact and efficient FPGA implementation of AES with 32-bit data-path has been proposed.•The proposed design utilizes data path compression and Galois field implementation of the s-box to minimize resource consumption.•With 595 slices and 2.004 Gbps throughput, AES-32GF cipher achieves an efficiency of 3.37 Mbps/slice.

FPGA-based neural network accelerators for millimeter-wave radio-over-fiber systems.

With rapidly developing high-speed wireless communications, the 60 GHz millimeter-wave (mm-wave) frequency range has attracted extensive interests, and radio-over-fiber (RoF) systems have been widely investigated as a promising solution to deliver mm-wave signals. Neural networks have been proposed and studied to improve the mm-wave RoF system performances at the receiver side by suppressing both linear and nonlinear impairments. However, previous studies of neural networks in mm-wave RoF systems all focus on the use of off-line processing with high-end GPUs or CPUs, which are not practical for low power-consumption, low-cost and limited computation platform applications. To solve this issue, in this paper we investigate neural network hardware accelerator implementations for mm-wave RoF systems for the first time using the field programmable gate array (FPGA), taking advantage of the low power consumption, parallel computation, and reconfigurablity features of FPGA. Both the convolutional neural network (CNN) and binary convolutional neural network (BCNN) hardware accelerators are demonstrated. In addition, to satisfy the low-latency requirement in mm-wave RoF systems and to enable the use of low-cost compact FPGA devices, a novel inner parallel computation optimization method for implementing CNN and BCNN on FPGA is proposed. It is shown that compared with the popular embedded processor (ARM Cortex A9) execution latency, the proposed FPGA-based hardware accelerator reduces the processing delay in mm-wave RoF systems by about 99.45% and 92.79% for CNN and BCNN, respectively. Compared with non-optimized FPGA implementations, results show that the proposed inner parallel computation method reduces the processing latency by about 44.93% and 45.85% for CNN and BCNN, respectively. In addition, compared with the GPU implementation, the latency of CNN implementation with the proposed optimization method is reduced by 85.49%, while the power consumption is reduced by 86.91%. Although the latency of BCNN implementation with the proposed optimization method is larger compared with the GPU implementation, the power consumption is reduced by 86.14%. The demonstrated FPGA-based neural network hardware accelerators provide a promising solution for mm-wave RoF systems.

Compact and Flexible FPGA Implementation of Ed25519 and X25519

This article describes a field-programmable gate array (FPGA) cryptographic architecture, which combines the elliptic curve--based Ed25519 digital signature algorithm and the X25519 key establishment scheme in a single module. Cryptographically, these are high-security elliptic curve cryptography algorithms with short key sizes and impressive execution times in software. Our goal is to provide a lightweight FPGA module that enables them on resource-constrained devices, specifically for Internet of Things (IoT) applications. In addition, we aim at extensibility with customisable countermeasures against timing and differential power analysis side-channel attacks and fault-injection attacks. For the former, we offer a choice between time-optimised versus constant-time execution, with or without Z -coordinate randomisation and base-point blinding; and for the latter, we offer enabling or disabling default-case statements in the Finite State Machine (FSM) descriptions. To obtain compactness and at the same time fast execution times, we make maximum use of the Digital Signal Processing (DSP) slices on the FPGA. We designed a single arithmetic unit that is flexible to support operations with two moduli and non-modulus arithmetic. In addition, our design benefits in-place memory management and the local storage of inputs into DSP slices’ pipeline registers and takes advantage of distributed memory. These eliminate a memory access bottleneck. The flexibility is offered by a micro-code supported instruction-set architecture. Our design targets 7-Series Xilinx FPGAs and is prototyped on a Zynq System-on-Chip (SoC). The base design combining Ed25519 and X25519 in a single module, and its implementation requires only around 11.1K Lookup Tables (LUTs), 2.6K registers, and 16 DSP slices. Also, it achieves performance of 1.6ms for a signature generation and 3.6ms for a signature verification for a 1024-bit message with an 82MHz clock. Moreover, the design can be optimised only for X25519, which gives the most compact FPGA implementation compared to previously published X25519 implementations.

Multichannel FPGA-Based Data-Acquisition-System for Time-Resolved Synchrotron Radiation Experiments

The aim of this contribution is to describe our recent development of a novel compact field-programmable gate-array (FPGA)-based data acquisition (DAQ) system for use with multichannel X-ray detectors at synchrotron radiation facilities. The system is designed for time resolved counting of single photons arriving from several—currently 12—independent detector channels simultaneously. Detector signals of at least 2.8 ns duration are latched by asynchronous logic and then synchronized with the system clock of 100 MHz. The incoming signals are subsequently sorted out into 10 000 time-bins where they are counted. This occurs according to the arrival time of photons with respect to the trigger signal. Repeatable mode of triggered operation is used to achieve high statistic of accumulated counts. The time-bin width is adjustable from 10 ns to 1 ms. In addition, a special mode of operation with 2 ns time resolution is provided for two detector channels. The system is implemented in a pocket-size FPGA-based hardware of 10 cm $\times 10$ cm $\times 3$ cm and thus can easily be transported between synchrotron radiation facilities. For setup of operation and data read-out, the hardware is connected via USB interface to a portable control computer. DAQ applications are provided in both LabVIEW and MATLAB environments.

Low-Temperature Monolithic Three-Layer 3-D Process for FPGA

We developed a wafer-scale, monolithic, 3-D integrated circuit process that features three active layers: a silicon base layer with CMOS circuitry, a second layer of germanium (Ge) PMOS devices, and a top layer of AlOxNy resistive random access memory (RRAM) cells. The temperatures of all processes, following the fabrication of the CMOS circuitry, are below 400°C to ensure no damage to the CMOS circuitry. The Ge layer is applied as an array of islands using low-temperature aligned bonding, followed by cleaving at the buried layer of implanted hydrogen ions. The Ge PMOS devices are lithographically aligned to the underlying CMOS and feature metal gates over high-κ dielectric. The RRAM devices built into the third layer exhibit sub-μA switched currents. This process is attractive for a compact field-programmable gate array with reduced area, delay, and power.

Compact field programmable gate array (FPGA)-based multi-axial interferometer for simultaneous tilt and distance measurement in the sub-nanometre range

Quantitative determination of microstructure and nanostructure properties is essential in research, development and in control of the production process. In instruments for dimensional nanometrology the positioning stage is the key component, since the characteristics of the position acquisition and control determine directly the achievable precision of the complete system. Compact commercial positioning systems usually employ capacitive or inductive position sensors. Both technologies not only offer a resolution in the nanometre range, but also require a (periodic) calibration. To achieve traceable measurements, interferometric sensors need to be implemented into the metrology system. However, currently available commercial interferometers turned out to be too large to be installed in miniature positioning stages easily. Therefore, a new highly compact interferometer to allow for traceability and an uncertainty in the Ångstrom range was developed. One of its first applications will be the new metrological low-noise atomic force microscope at the Physikalisch-Technische Bundesanstalt. The new interferometer is based on a modified homodyne Twyman–Green interferometer concept. It uses a novel signal processing approach based on a field programmable gate array, whereby a spatial interferogram is acquired by a high-speed CMOS line sensor and transformed into its frequency spectrum through a discrete Fourier transform. The spectral representation is analyzed for its major components; the phase information bears a direct connection to the displacement of the positioning unit. Furthermore, a possible stage tilt during the scan gives rise to a shift of the peak magnitude in the frequency spectrum. In addition, the developed system proved to be easily extendable to multiple axes by superimposing multiple interferograms on a single line sensor.

A VHDL Holistic Modeling Approach and FPGA Implementation of a Digital Sensorless Induction Motor Control Scheme

This paper presents a sensorless neural-network-based induction motor control scheme, developed by following a holistic approach to electronic system modeling and controller design. The method uses very-high-speed integrated circuits hardware description language (VHDL), allowing the engineering system's functional description to be combined with a detailed digital controller design, which is then implemented into a field- programmable gate array (FPGA). The VHDL description of the hardware-implemented neural networks is automatically generated by C++ programs, in an adaptable architecture, appropriate to low-dynamic systems such as fans and pumps. The complete system performance is investigated by simulation and validated experimentally. This approach provides advantages such as a unique modeling and evaluation environment for complete power electronic systems, the same environment is used for the digital controller design and compact FPGA rapid prototyping, fast design development, short time to market, a CAD platform independent model, and reusability of the model/design