Reduced Common Mode Voltage PWM Research Articles

Analysis and Measurement of Non-Intrinsic Differential-Mode Noise in a SiC Inverter Fed Drive and Its Attenuation Using a Passive Sinusoidal Output EMI Filter

The analysis, measurement, and attenuation of non-intrinsic differential-mode (NDM) and common-mode (CM) noise in an induction motor (IM) drive are discussed in this paper. In a voltage source inverter (VSI) fed drive, the NDM noise is caused by the excitation of the CM capacitance paths by the line to ground voltage. A measurement method at the input side of IM is proposed to separate intrinsic differential-mode (IDM), NDM, and CM noise from the total line current. It is substantiated that the NDM noise constitutes a significant portion of the measured DM noise. Hence, a passive sinusoidal output electromagnetic interference (EMI) filter (PSOEF) is presented to attenuate the NDM and CM noise. PSOEF is designed using line inductor & capacitor with the same resonance frequency to attenuate the NDM and CM noise. PSOEF has an advantage of reduced size and number of CM components as compared to conventional sinusoidal output EMI filter (CSOEF). The designed PSOEF is presented with space vector pulse width modulation (PWM) and CM voltage reduction PWM to analyze the attenuation performance, circulating current, and filter loss. The proposed measurement method and the design of PSOEF are experimentally validated on a SiC VSI switching at 200 kHz.

An optimal zero‐sequence voltage injection‐based common‐mode voltage reduction pulse‐width modulation for the reduction of common‐mode voltages in both amplitude and third‐order component

An optimal zero-sequence voltage injection-based common-mode voltage reduction pulse-width modulation (CMVRPWM) for the reduction of common-mode voltages (CMVs) in both amplitude and third-order component is proposed in this paper. On the basis of general symmetrical switching patterns of CMVRPWM, a constrained mathematical programming model is established with the objective of optimizing the volt-second value of CMV in each switching period. By solving the mathematical model, the limitation of the CMV amplitude and the reduction of third-order harmonic in CMV can be achieved simultaneously, contributing to better CMV suppression and common-mode filter design in the applications of two-level voltage source inverters (2L-VSIs). The optimal zero-sequence voltage under the given target is obtained, and the calculation method of the switching pattern and modulation wave is studied. Simulation and experimental results show that the proposed method can restrict the CMV amplitude within one-sixth of the DC bus voltage, and the third-order component in CMV is effectively reduced compared with the conventional methods.

Optimal Current Ripple PWM for Three-Level Inverter With Common Mode Voltage Reduction

Three-level inverter has been widely used in electric drives and renewable power generation system. However, the common mode voltage (CMV) and output current ripple reduction of three-level inverter should be carefully regulated for the appropriate operation. As these two targets are mutually interrelated, the conventional space vector modulation (SVM) scheme cannot cope with them decently. To overcome this drawback, this paper proposes a novel modified SVM scheme to realize CMV and current ripple reduction simultaneously. The generating mechanism of output current ripple is analyzed, and the relationship between current ripple and utilized vectors is quantitatively described. Based on the analyses, the proposed optimal current ripple and CMV reduction pulse width modulation (OCR-CMVRPWM) method adopts four voltage vectors (large, medium, small and zero vectors) to reduce root mean square (RMS) value of current ripple by allocating the sequence and dwell times of utilized vectors. Compared to the existing PWM methods, the proposed OCR-CMVRPWM scheme can reduce the peak of CMV to half of value using the conventional SVM, and obtain a significant reduction of output current total harmonic distortion (THD). The effectiveness of the proposed method is validated by both simulation and experimental results.

Performance Analysis and Experimental Validation of 240°-Clamped Space Vector PWM to Minimize Common Mode Voltage and Leakage Current in EV/HEV Traction Drives

High switching frequency inverters in hybrid electric vehicle/electric vehicle (HEV/EV) drivetrains present problems such as common mode voltage (CMV) and leakage current that have negative impacts on the performance of the drivetrain. Various reduced CMV PWM (RCMV-PWM) methods have been introduced in the literature that reduces the CMV but typically at the expense of increased total harmonic distortion (THD) and switching loss simultaneously. In this article, a low-loss PWM method called 240°-clamped space vector PWM (240CPWM) is discussed in terms of its CMV and leakage current characteristics. It is analytically shown that 240CPWM reduces the peak CMV and the number of CMV pulses in a switching period by 66.7% each, and RMS CMV by 21%, while simultaneously reducing the switching loss by 85%, and achieving similar THD at maximum speed (and lower THD at other speeds) as compared to conventional space vector PWM (CSVPWM). Detailed analysis of CMV and leakage current is presented for 240CPWM and compared with CSVPWM and discontinuous PWM (DPWM1) with constant and variable dc-link voltage control. Experimental results from a 10-kW hardware prototype are presented that conform to the analytical discussions and validate the superior performance of 240CPWM.

An Improved Simplified PWM for Three-Level Neutral Point Clamped Inverter Based on Two-Level Common-Mode Voltage Reduction PWM

In this article, a common-mode voltage reduction pulsewidth modulation (CMV-R PWM) for three-level neutral point clamped inverter based on the simplification of the three-level space–vector diagram into that of a two-level inverter is studied. By replacing the switching sequence of two-level space–vector PWM with that of CMV-R PWM, the common-mode voltage of the proposed method can be restricted to one-sixth of the dc-link voltage. With the new switching sequences, the neutral-point voltage control by calculating an optimized injected zero-sequence voltage is introduced. Simulation and comparative analysis is given to illustrate the features of the proposed method. The effectiveness and correctness of the proposed method is verified by experiment.

Fast-Processing Implementation of Current-Ripple-Losses-Optimized Common-Mode Voltage Reduction PWM

In this paper, a fast-processing implementation method of the current-ripple-loss-optimized common-mode voltage reduction pulsewidth modulation (CRLO-CMVRPWM) is studied. With the novel sector definitions and the simplified method to solve the constraint nonlinear programming model, the compute burden of the proposed method is reduced by 82.8% and 50.5% for the case where the modulation index is below and above $4\sqrt 3 /9$ , respectively. In addition, the effects of the optimized zero-sequence voltage errors caused by the adopted linear fitting strategy are proven to be negligible by studying the harmonic characteristics difference between the fast-processing and original CRLO-CMVRPWM. Simulated and experimental results are given to validate the effectiveness.

High-Frequency SiC Three-Phase VSIs With Common-Mode Voltage Reduction and Improved Performance Using Novel Tri-State PWM Method

Common-mode voltage (CMV) problem brings severe negative effects in three-phase voltage source inverters (VSIs), particularly for high-frequency silicon (Si) carbide (SiC) VSIs. However, most traditional CMV reduction strategies, which are studied based on Si VSIs, are hard to be implemented and sacrifice the other performance of the VSIs. To overcome such drawbacks, this paper proposes a novel generalized tri-state pulsewidth modulation (GTSPWM) for high-frequency SiC VSIs over power factor of 0–1 and whole linear modulation index range. The working principle of conventional space vector based reduced CMV PWM (RCMV-PWM) methods are reviewed, and their switching signals and CMV patterns are illustrated. The proposed GTSPWM method is described in a generalized scalar PWM approach for simple application and compared with other RCMV-PWM methods. Mathematical analysis, simulations, and experimental results have been used to verify that GTSPWM based high-frequency SiC VSIs can achieve minimum switching losses, improved output waveform quality, smaller dc-link current ripples, and RCMV characteristics. Moreover, with the usage of GTSPWM method, the switching frequency of SiC VSIs can be further increased, and the performance of high-frequency SiC VSIs could be improved appreciably.

A New Active Zero State PWM Algorithm for Reducing the Number of Switchings

To reduce common-mode voltage (CMV), various reduced CMV pulse width modulation (RCMV-PWM) algorithms have been proposed, including active zero state PWM (AZSPWM) algorithms, remote state PWM (RSPWM) algorithms, and near state PWM (NSPWM) algorithms. Among these algorithms, AZSPWM algorithms can reduce CMV, but they increase the number of switchings compared to the conventional space vector PWM (CSVPWM). This paper presents a new AZSPWM algorithm for reductions in both the CMV and total number of switchings in BLAC motor drives. Since the proposed AZSPWM algorithm uses only active voltage vectors for motor control, it reduces CMV by 1/3 compared to CSVPWM. The proposed AZSPWM algorithm also reduces the total number of switchings compared to existing AZSPWM algorithms by eliminating the switchings required from one sector to the next. The performance of the proposed algorithm is verified by analyses, simulations, and experimental results.

Review on pulse‐width modulation strategies for common‐mode voltage reduction in three‐phase voltage‐source inverters

With wide application of inverters in modern industry, common-mode voltage (CMV) problems invoked severe negative effects. Hardware and software solutions have been proposed to reduce the CMV. Compared with hardware CMV mitigation solutions, software strategies based on pulse-width modulation (PWM) modifications have aroused widespread attention for their cost-effective and control flexible advantages. Up to date, various reduced CMV PWM (RCMV-PWM) strategies have been reported, such as active zero state PWM, remote state PWM, near state PWM, phase-shifted carrier PWM, carrier peak position modulation and so on. For convenience of understanding and utilising the existed RCMV-PWM strategies, this study conducts a review on this topic. According to the principle of CMV reduction algorithms, the study divides the reported RCMV-PWM strategies into three different categories. It also presents comparisons of CMV reduction techniques and output performances (like CMV value, output ripple and linearity range) between different strategies. Meanwhile, CMV suppression principles, problems in implementation and improvements of each technique are described in detail. Moreover, the inherent characteristics and development tendencies of the RCMV-PWM techniques are discussed so as to offer reference for further research.

Evaluation of PWM Methods for Suppressing Circulating Current Among Parallel-Connected Four-Pole Inverters

This paper investigates the effects of pulse width modulation (PWM) on the circulating current of parallel-connected four-pole inverters (FPIs). Detailed mathematical modeling shows that the common-mode voltage (CMV) outputs of PWMs are closely related to the circulating current, so this research presents the reduced CMV PWM techniques for FPIs to reduce the circulating current, and compares their performances with the conventional PWM schemes. This study also shows how the controller structure of FPI affects the use of PWM schemes and the resulting circulating current. Laboratory test results are provided to validate their effectiveness.

A Generalized Algorithm to Eliminate Spikes of Common-Mode Voltages for CMVRPWM

This paper presents a generalized algorithm to eliminate spikes of common-mode voltages (CMV) caused by dead-time effect for common-mode voltage reduction pulse width modulation (CMVRPWM). The characteristics of the CMV spikes for the popular CMVRPWM strategies (AZSPWM1, NSPWM, CRLO-CMVRPWM, and SLO-CMVRPWM) are studied and compared by analyzing the extreme switch pulse patterns. The proposed CMV spikes elimination method directly adjusts the injected zero-sequence voltages instead of the durations of the adopted voltage space vectors to avoid the overlaps of the adjacent dead time periods. The CMV spikes can be eliminated regardless of the output voltages in the dead time periods; thus, the signs of phase currents are not needed to detect and overcome the problem caused by the resolution of the current sensors when the phase currents approach to zero. In addition, an effective method by online selecting low or high active pulses for the three legs is proposed to ensure that at most one leg switches between adjacent carrier periods. The proposed method is generalized and effective for all the CMVRPWM with symmetrical switch pulse patterns and no simultaneous switching problem. The simulation and experimental results validate the effectiveness.

Optimized Common-Mode Voltage Reduction PWM for Three-Phase Voltage-Source Inverters

In this paper, two new optimized common-mode voltage reduction PWM (CMVRPWM) strategies based on solving the established constrained nonlinear programming models in the time domain are proposed and analyzed. The proposed current ripple losses-optimized CMVRPWM (CRLO-CMVRPWM) minimizes the mean-square values of the three-phase current ripples by calculating the optimized special solutions of the voltage–second balance equations under the designed switching sequences. CRLO-CMVRPWM can achieve better output waveform quality than the existing methods. The proposed switching losses-optimized CMVRPWM (SLO-CMVRPWM) online optimizes the bus-clamping styles according to the phase currents to minimize the switching losses under different load power factors. Compared to the near-state PWM with fixed bus-clamping styles, SLO-CMVRPWM can reduce more switching losses in broader range of the modulation index. Simulation and experimental results verify the superiority of the proposed strategies to the conventional ones.

Bearing Currents and Shaft Voltage Reduction in Dual-Inverter-Fed Open-End Winding Induction Motor With Reduced CMV PWM Methods

Exploiting the rich switching redundancies of the dual inverter, new hybrid pulsewidth-modulation (PWM) switching methods are proposed in this paper using the degree of freedom of operating the individual inverters independently, in addition to exercising the degree of freedom of controlling the switching action of the individual legs independently. Two voltage entities, namely, common-mode voltage (CMV) and differential-mode voltage are identified in the dual inverter, and all hybrid PWMs are envisaged aimed at reducing and also eliminating the CMV in it. The effects of such attempts on motor shaft voltage and also the motor bearing currents are presented in detail. Furthermore, bearing current profiles of an open-end winding induction motor are also presented with both conventional and hybrid PWMs proposed in this paper. Electric discharge machining discharge currents are completely eliminated with the use of all hybrid PWM methods proposed in this paper. In addition, implications of completely eliminating the CMV are also presented in this paper. All hybrid PWMs proposed in this paper are first simulated using MATLAB and are experimentally verified on a dual two-level inverter feeding a 1.1-kW 415-V 3-φ open-end winding induction motor drive.

Common-Mode Voltage Reduction Pulsewidth Modulation Techniques for Three-Phase Grid-Connected Converters

This paper experimentally investigates the performance of three-phase voltage source pulsewidth modulation (PWM) converter, with the grid interfaced photovoltaic energy conversion system being the main application. In such applications the ground leakage current [common mode current (CMC)] should be much less than an ampere and this is difficult to obtain in transformerless (direct) connected systems. With the target being the reduction of the common mode voltage (CMV) and CMC, the converter performance is investigated thoroughly. Conventional PWM methods [space vector PWM (SVPWM) and discontinuous PWM (DPWM)] and recently developed reduced common mode voltage PWM (RCMV-PWM) methods [active zero state PWM (AZSPWM) and near state PWM (NSPWM)] are considered. The performance of a 1-kW rated PWM rectifier with additional common-mode capacitor emulating a PV system has been experimentally investigated. It is shown that the CMV and CMC of the tested RCMV-PWM methods is significantly less than conventional methods. In particular, NSPWM yields the best overall performance including low ground leakage current, low inverter output (phase current) and input (dc-link current) ripple, and low switching losses. Accounting for the parasitic capacitance effect, the resonant frequency of the common-mode circuit is identified and it is used in the converter design for the purpose of avoiding resonances involving large CMV-CMC. This paper aims help the design engineer select the appropriate PWM method for grid-connected applications and provides some design rules of thumb.

A High-Performance PWM Algorithm for Common-Mode Voltage Reduction in Three-Phase Voltage Source Inverters

A high-performance pulsewidth modulation (PWM) algorithm with reduced common-mode voltage (CMV) and satisfactory overall performance is proposed for three-phase PWM inverter drives. The algorithm combines the near-state PWM (NSPWM) method that has superior overall performance characteristics at high modulation index, and MAZSPWM, a modified form of the active zero-state PWM method (AZSPWM1), which is suitable for low modulation index range of operation. Since AZSPWM1 has line-to-line voltage pulse reversals with small zero-voltage time intervals, in its naive form, it causes overvoltages, in particular in long-cable motor drive applications. Obtained by reorganizing the duty cycles of the utilized voltage vectors of AZSPWM1, MAZSPWM has sufficiently long zero-voltage time intervals between pulse reversals such that during pulse reversals, overvoltages are avoided. The combined algorithm performs satisfactorily throughout the inverter operating range and the transition from NSPWM to MAZSPWM and vice versa is seamless. The performance of the proposed algorithm is proven by theory, computer simulations, and detailed laboratory experiments. The paper also shows that the proposed reduced CMV PWM algorithm is effective in reducing the motor leakage current, and it is most beneficial when a small common-mode inductor is included in the drive.

Performance Analysis of Reduced Common-Mode Voltage PWM Methods and Comparison With Standard PWM Methods for Three-Phase Voltage-Source Inverters

This paper surveys the reduced common-mode voltage pulsewidth modulation (RCMV-PWM) methods for three-phase voltage-source inverters, investigates their performance characteristics, and provides a comparison with the standard PWM methods. PWM methods are reviewed, and their pulse patterns and common-mode voltage (CMV) patterns are illustrated. The inverter input and output current ripple characteristics and output voltage linearity characteristics of each PWM method are thoroughly investigated by analytical methods, simulations, and experiments. The research results illustrate the advantages and disadvantages of the considered methods, and suggest the utilization of the near-state PWM and active zero state PWM1 methods as overall superior methods. The paper aids in the selection and application of appropriate PWM methods in inverter drives with low CMV requirements.

Optimal Common-Mode Voltage Reduction PWM Technique for Inverter Control With Consideration of the Dead-Time Effects—Part I: Basic Development

The objective of this paper is to investigate the optimal common-mode voltage reduction pulsewidth modulation (PWM) technique when dead-time effect is taken into account. The effect of dead time on common-mode voltage for inverter control and the associated solution are discussed. Based upon these results, an optimal common-mode voltage reduction PWM technique, which requires no extra voltage/current sensors and compensation mechanism while not being affected by the dead time, is recommended. The common-mode voltage can be reduced to one-third for the inverter with diode front end, which is widely used in industry. Intensive measured results are presented to fully support the claims.

Optimal Common-Mode Voltage Reduction PWM Technique for Inverter Control With Consideration of the Dead-Time Effects—Part II: Applications to IM Drives With Diode Front End

The main theme of this paper is to demonstrate the applications of the newly developed common-mode voltage reduction pulsewidth-modulation (PWM) technique, which restricts the common-mode voltage to one-third of DC-link voltage, to vector-controlled induction motor drives. As compared to previous common-mode voltage reduction techniques, the presented technique can be applied to the inverter with diode front end and has no adverse effect on the linear modulation range. Therefore, vector-controlled drives using the developed technique for inverter control have a wide speed range. Moreover, the effects of the common-mode voltage reduction PWM technique on speed response for vector-controlled induction motor drives will be fully investigated in this paper. It will be demonstrated by intensive experimental results that speed performance does not deteriorate significantly within the rated speed range.