Common-mode Voltage Elimination Research Articles

A Common-Mode Voltage Elimination Scheme by Reference Voltage Decomposition for Back-to-Back Two-Level Converters

Common-mode voltage (CMV) can greatly reduce the reliability and performance of back-to-back two-level converter-fed motor drive systems. To address this issue, a novel CMV elimination scheme based on reference voltage decomposition is proposed in this article. Firstly, the reference voltage of each phase is decomposed into two virtual reference voltages, resulting in six virtual reference voltages that are inter-related for back-to-back two-level converters. Then, by comparing each virtual reference voltage with a triangle carrier based on the two-level pulse width modulation (PWM), the final PWM voltage of each phase can be obtained from the differences of the corresponding two virtual PWM outputs. With the proposed method, both the amplitude and RMS value of CMV can be eliminated theoretically with satisfactory output waveform qualities. Simulations and experimental results are presented to verify the proposed method.

A Discrete Selective Harmonic Elimination Formulation With Common-Mode Voltage Elimination Ability

A Discrete Selective Harmonic Elimination Formulation With Common-Mode Voltage Elimination Ability

Common-Mode Voltage Elimination of Multilevel Converters With Reduced Switching Loss Using Sawtooth-Carrier-Based PWM

This paper proposes an asymmetrical switching pattern to eliminate common-mode voltage (CMV) in multilevel converters while reducing switching loss by rearranging the switching sequence to minimize the number of level-shifts. In contrast to the existing symmetrical switching pattern, this approach achieves CMV elimination without increasing switching loss. To implement this asymmetrical switching pattern, a simple sawtooth carrier-based PWM scheme is proposed that avoids the need for complicated space vector modulation (SVM) computation, particularly for high-level converters. The proposed method's effectiveness is demonstrated through simulations and experimental results for the three-phase cascaded H-bridge converter and boost seven-level active neutral-point-clamped converter.

A CB-PWM Technique for Eliminating CMV in Multilevel Multiphase VSI

A generalized Carrier-Based Pulse Width Modulation (CB-PWM) scheme is proposed here for the elimination of common-mode voltage (CMV) in a multilevel multiphase voltage source inverter (VSI). In this CB-PWM scheme, the switching function of x-level, q-phase VSI is obtained from the switching function of virtual y-level and (y+1) level, q-phase VSI, where y = (x+1)/2 when x is odd and y = x/2 when x is even. It is established here that the pole voltages of q-phase x-level VSI thus obtained generate zero CMV. The proposed CB-PWM technique is computationally less intensive and hence can be easily implemented in hardware. Extensive simulation and experimental results are presented to validate the proposed CMV elimination technique in 3-phase 7-level VSI, 5-phase 5-level VSI, and 6-phase 4-level VSI. A comparative study of the proposed PWM scheme with the existing technique shows the superiority of the proposed technique in eliminating CMV.

Quasi Z-Source Neutral-Point-Clamped Inverter Using SVM Technique to Eliminate Common Mode Voltage

In recent year, common mode voltage (CMV) elimination methods are considered to improve the reliability of three-level quasi-switched boost T-type inverter (TL-qSBT2I). The space-vector modulation method (SVM) can control the inverter operation to eliminate the CMV. The proposed method applies medium vectors and zero vector to synthesize the reference vector to eliminate CMV while the output voltage is unchanged compared to SinPWM technique. In order to prevent the active vectors and the output voltage from being affected, the shoot-through vector is inserted inside the zero vector. Accordingly, the proposed method not only maintains the CMV elimination advantage of the SVM technique for TL-qSBT2I but also reduces the inductor current ripple and enhances the voltage gain without any topology modification or adding electrical components. Results from simulations and experiments are used to evaluate the efficiency of the suggested strategy. Additionally, by comparing the proposed scheme with the traditional pulse-width modulation technique, the superiority of the proposed scheme is shown.

Common Mode Voltage Minimization for Generalized Dual Inverter-Fed Aircraft Starter/Generator: Realization and Sub-Load Asymmetry Influence Analysis

In multi-stages aircraft starter/generator system, the main machine (MM) and main exciter (ME) are fed by a generalized dual-inverter configuration, allowing for common-mode voltage (CMV) elimination. However, the distinction in load impedances and voltage requirements between the two sub-inverters has evidently contributed to the sub-load asymmetry, which may impair the suppression effect of system common mode (CM) noises. This paper presents a CMV minimization method for the generalized dual-inverter application. The available freedom, such as the selection and action sequence of voltage vectors, is appropriately arranged in the suggested implementation to eliminate the total CMV, restrict the sub-CMVs and fulfill the voltage requirements of sub-inverters all at the same time. In the meanwhile, a theoretical study is performed to evaluate the CM noise features of zero CMV technique in the generalized dual inverter-fed system. In the situation of sub-load asymmetry, the premise and main influence element for CM noise reduction are assessed. Finally, these findings are verified by simulation and experiments.

A Space Vector Based Zero Common-Mode Voltage Modulation Method for a Modular Multilevel Converter

A modular multilevel converter (MMC) can generate different common-mode voltage (CMV) values due to the high-frequency changing of the switching state under various modulation strategies. The high-frequency dv/dt will produce common-mode current in the equivalent common-mode loop to the ground, which will affect the insulation and shorten the life of the equipment. To eliminate the effect of common-mode voltage on MMC operation, a common-mode voltage elimination strategy (0CMV-SVPWM) is proposed for five-level MMC space vector pulse width modulation (SVPWM) by using the vector that does not generate common-mode voltage as the reference vector in this paper. The proposed strategy is studied and analyzed by the rapid prototype development experimental system based on RT-LAB to verify the feasibility and effectiveness of the proposed strategy.

Novel Common Mode Voltage Elimination Methods in Three-Phase Four-Wire Grid-Connected Inverters

This paper presents two current control methods to attenuate the common mode (CM) conducted emissions in three-phase four-wire four-pole inverters connected to an AC distribution bus and operating in grid-following mode. Delta modulation and model predictive control both achieve elimination of the common mode voltage at the output of the three-phase four-pole inverter and meet the requirements of the military standard 461G without a full-size CM choke. The differential mode performance is comparable to that achieved with the benchmark three-dimensional space vector modulation, which does not cancel the CM voltage. A physics-based model of the system was developed to simulate the conducted emissions and DM performance of the two proposed methods. As the CM voltage cancellation methods result in increased switching frequency, wide bandgap devices were used to build a laboratory prototype, on which the simulated results were successfully validated.

Current-Balance Mode-Based Unified Common-Mode Voltage Elimination Scheme for Dual Three-Phase Motor Drive System

The two-level voltage source inverter fed dual three-phase motor (DTPM) induces the high-frequency common-mode voltage (CMV) and generates the unwanted adverse effects. As one of the effective common-mode suppression methods, the conventional CMV elimination (CMVE) pulsewidth modulation (PWM) schemes are generally based on the voltage-balance mode for DTPM systems which suffer from the parameter asymmetry induced phase current imbalance. This article proposes two current-balance mode unified CMVE PWM schemes which has no restriction on the reference voltages and angle displacement between the two sets of three-phase windings. Thus, the proposed methods can be utilized in different types of DTPMs with different angle displacements between the two winding sets, and the CMVE effect can be retained both in the conditions of symmetrical and asymmetrical system parameters which is more practical than conventional CMVE schemes in real application. The function and performance of the proposal is proved by simulations and experiments.

A Common-Mode Voltage Elimination Method With Active Neutral Point Voltage Balancing Control for Three-Level T-Type Inverter

Nowadays, the three-level T-type inverters (3LT2Is) are widely employed in applications with high-performance requirements. The 3LT2Is commonly suffer from neutral point voltage (NPV) unbalance and common-mode voltage (CMV) variation. The medium vector pulse width modulation (MVPWM), which generates the reference voltage using medium and V0[OOO] zero voltage vectors, eliminates the CMV variation in 3LT2Is. However, it cannot keep the NPV balance, negatively affecting power quality. This article proposes a hybrid method to simultaneously eliminate CMV variation and guarantee the NPV balance without topological change or extra hardware. The proposed method uses MVPWM when NPV is balanced, eliminating CMV variation. If NPV goes unbalanced, it utilizes novel high/low triangle PWM (H/LPWM) and MVPWM in a hybrid manner to balance the NPV. The H/LPWM, similar to MVPWM, synthesizes voltage using medium and V0[OOO] voltage vectors to maintain the CMV elimination advantage during the NPV balancing process. However, the difference between H/LPWMs and MVPWM switching patterns adjusts the average neutral point current to balance the NPV. Noteworthy that the proposed method provides NPV balancing ability for the entire power factor range. As a result, it is usable for various applications of 3LT2I, such as photovoltaic inverters and motor drives. The proposed method is carrier-based, which reduces the execution time and simplifies the practical implementation. The simulation study and experimental evaluation have been accomplished, and their results demonstrate the effectiveness of the proposed method.

Direct torque control of three-level five-phase inverter-fed five-phase induction motor with common-mode voltage elimination

Direct torque control of three-level five-phase inverter-fed five-phase induction motor with common-mode voltage elimination

Elimination of Dead Time Effects on Common Mode Voltage in an Open-End Winding Induction Motor Drive Under Low Speed Operation Using a Simplified Model Predictive Control

In this article, a simplified model predictive current control (MPCC) for a three-level open-end winding induction motor drive mitigating the dead time effects on common mode voltage (CMV) in the low speed operation of the motor is proposed. The traditional current based objective function is replaced with an equivalent voltage based objective function, and an additional term indicating the nonzero CMV during dead time is added to achieve complete CMV elimination. Further, a sector-based selection of candidate switching states is employed to reduce the computational burden. It is also shown that the constraint on eliminating the dead time effect on CMV heavily deteriorates the performance of the drive at higher speeds and a smooth transition with and without the constraint is also demonstrated. The envisaged MPCC is simulated in MATLAB and is experimentally verified using TMS320F28377S launchpad. The proposed MPCC gives a massive reduction in the computational burden compared to the conventional MPCC without sacrificing the motor drive performance.

Bidirectional H8 AC–DC Topology Combining Advantages of Both Diode-Clamped and Flying-Capacitor Three-Level Converters

A three-level bidirectional ac–dc converter with H8 topology is proposed to combine the advantages of both neutral-point clamped and flying-capacitor (FC) three-level converters for medium-voltage (MV) ac–dc solid-state transformer (SST) applications. The innovative H8 converter features self-balanced capacitor voltage, common-mode voltage elimination, and small capacitance of the FCs. The proposed carrier-based modulation enables the H8 converter to operate under both active and reactive power conditions. A 10-kVA ac–dc converter prototype with 1.7-kV SiC MOSFETs and 3.3-kV SiC diodes verifies the feasibility and advantages of the proposed topology and the modulation method. The capacitance of the FCs in the H8 converter is reduced by 45 times compared to that of the FC converters. The H8 converter efficiency is tested up to 99% at 2-kV dc voltage. The proposed H8 converter is suitable for the next-generation PV inverter, grid-forming inverter, MV fast charger, and SST applications.

Common-Mode Voltage Mitigation of Dual T-Type Inverter Drives Using Fast MPC Approach

This article proposes an intensive study for common-mode voltage (CMV) elimination/reduction in a five-level dual T-type multilevel converter (MLC) drive. An advanced and fast model predictive control (MPC) approach is developed for CMV reduction (CMVR) and CMV elimination based on the preselection of the switching states (SS). In addition, the proposed approach considers the torque control and the capacitor balancing of the proposed drive as essential aspects of MLC drives. A detailed study of the impact of the converter SS on the CMV is presented. The main features of the proposed MPC approach are reducing the complexity of the cost-function, the tuning burden of the weighting factors, and the computation time by more than 80% compared to conventional MPC techniques. A hardware implementation based on Silicon Carbide T-type MLC is built. The experimental results demonstrate the effectiveness of the proposed MPC approach to mitigate/eliminate the CMV along with achieving the torque command and balancing the dc-link capacitors. Unlike conventional CMVR techniques, the proposed approach reduces the CMV by 75% of its normal values without jeopardizing the harmonic contents, drive efficiency, and flux as well as torque ripples.

A Carrier-Based Common-Mode Voltage Elimination Method for Back-to-Back Three-Level NPC Converters

As the increase of power and voltage level of back-to-back three-level neutral-point clamped (NPC) converters, the high-amplitude and high-frequency common-mode voltage (CMV) has become an urgent problem. To address this, a CMV elimination method based on pulsewidth modulation pulse alignment for back-to-back three-level NPC converter is proposed. On this basis, a neutral-point potential balance method based on zero-sequence voltage (ZSV) is also proposed. In order to decouple the CMV elimination and the neutral-point potential balance, the same optimal ZSV is injected into both the rectifier and inverter sides, and the CMV elimination will not be affected. Simulation and experiments are presented to verify the effectiveness of the proposed method.

Robust Model Predictive Control for AFE-Inverter Drives With Common Mode Voltage Elimination

This paper proposes a novel and robust version of Model Predictive Control scheme for AC drives based on Voltage Source Inverter (VSI) with Active Front End (AFE). The main feature of the proposed MPC is elimination of Common Mode Voltage (CMV) without imposing a penalty on the corresponding term in the cost function, but rather by a smart utilisation of the restricted set of switching states in a computationally efficient algorithm. Furthermore, the paper proposes to split the conventional MPC scheme into separate Control and Modulation stages, and to enhance the Control stage by integral action, and the Modulation stage - by a Feedback Quantizer.

Reduction of common mode voltage for cascaded 3-level inverter using SVPWM

The common mode voltage (CMV) generated by multilevel inverters can be reduced. This paper presents a Spacevector pulse width modulation (SVPWM) approach for cascaded 3-level inverters to reduce common mode voltage. Conventional 3-level pulse width modulated (PWM) inverters are widely known for producing high-frequency commonmode voltages with high dv/dt. Motor shaft voltages and bearing currents can be caused by common mode voltages. In this work, to reduce common mode voltage, partial CMV elimination technique is used. In this method the redundant states of 3-level inverter having CMV less than or equal to Vdc/6 are only used and the redundant states having CMV greater than Vdc/6 are avoided by implementing SVPWM, where Vdc is the input DC voltage of inverter. A simulation of an dc SVM technique to reduce common mode voltage is implemented. Bearing voltages, bearing currents and total harmonic distortion (THD) are evaluated in the performance analysis. The results will prove the reduction of CMV with the proposed technique compared to conventional SVPWM.

Predictive Torque Control of Five-Phase Induction Motor Drive Using Successive Cost Functions for CMV Elimination

This article presents a predictive torque control (PTC) algorithm for a five-phase (distributed winding) induction motor fed by a three-level neutral-point-clamped inverter to remove the common-mode voltage (CMV). In this approach, a finite range of 31 voltage vectors (VVs) is chosen from the total available 243 VVs for the removal of the CMV. The xy-subspace current harmonic reduction is achieved with grouped VVs. The developed PTC algorithm has two successive cost functions: g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1h</sub> for stator flux and electromagnetic torque regulation and g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2h</sub> for xy-subspace current harmonic reduction. The purpose of these two successive cost functions is to reduce the complexity in determining the independent weighting factors. This algorithm retains the torque and flux responses similar to that of conventional PTC. The minimization in switching frequency is obtained in the presented PTC algorithm with the selected set of VVs. For evaluating and ascertaining the capabilities for CMV elimination and xy-subspace harmonic current reduction, the proposed algorithm is compared with the conventional PTC algorithm having a different set of VVs. Experimental outcomes show the significance of the discussed algorithm in the steady state and retain the transient operating conditions.

An improved method of model predictive current control for multilevel cascaded H-bridge inverters

Abstract Finite control set ModelPredictive control (FCS-MPC) with the principle of considering all voltage vectors to find the optimal voltage vector for multilevel inverter in a very small sampling cycle is hardly feasible because there is no modulation part, the implementation of optimizing common-mode voltage and switching number for the multilevel inverter should be performed in the cost function. To solve the above problem, this paper proposes an improved method of model predictive current control selecting 19 adjacent voltage vectors and using weighting coefficients for common-mode voltage elimination and switching optimization. By using a discrete-time model of the system to predict the future value of the current for the voltage vector in the previous sampling cycle and its 18 adjacent voltage vectors, the one that minimizes a cost function will be selected. Thus, in a multilevel inverter with any number of levels, the cost function is performed only 19 times in a sampling cycle. The computation on FPGA allows 19 calculations of the cost function to be performed in parallel, so the executing time is very small. The feasibility of the proposed algorithm is verified by simulation model on MATLAB-simulink software and the experimental 11-level cascaded H-bridge multilevel inverter model.

A novel PWM technique to eliminate common-mode voltage for single-phase three-level T-NPC inverter

This paper presents a new pulse width modulation (PWM) technique in order to eliminate common mode voltage for a single-phase full H-bridge T-NPC inverter. Three-level NPC inverters are commonly used in grid connected applications or as UPS backup power for industry. In addition to abilities such as to withstand high voltage, and reach output voltage and current with low harmonic distortion, three-level NPC inverter is advantageous for mitigating common mode voltage and leakage current. The new proposed PWM technique is based on the switching state table of the three-level H-bridge T-NPC inverter that containing many switching states with zero common mode voltage. Furthermore, implementation of PWM control for single-phase three-level T-NPC inverter configuration can decrease voltage stress on the output and reduce output voltage distortion compared with bipolar PWM control technique for two-level H-bridge inverter. In this paper, the sine wave carrier PWM technique is analyzed, designed and modelled based on the switching table. The analytical analysis will be evaluated using MATLAB/SIMULINK. Simulation results of the proposed PWM technique for three-level T-NPC inverter are compared with conventional techniques without common mode voltage elimination; the quality of the three-level T-NPC inverter is also compared to that of traditional two-level inverter. The power loss content is evaluated using PLECS software. The obtained results confirm the advantages of the eliminated common mode voltage PWM technique in the three-level T-NPC inverter configuration.