Input Common-mode Voltage Range Research Articles

Impact of Channel Implantation on a 4H-SiC CMOS Operational Amplifier for High Temperature Applications

In this work, the impact of channel implantations (IMP) on the electrical characteristics of SiC n-and p-MOSFETs and analog SiC-CMOS operational amplifiers (OpAmp) is investigated. For this purpose, MOSFETs and Miller OpAmps with and without IMP were fabricated and electrically characterized from room temperature up to 350°C. For devices with IMP the absolute values of the threshold voltages of n-and p-MOSFETs were reduced by 1.5 V and the mobility of the n-MOSFET was increased from 13 to 23 cm2/Vs whereas the mobility of the p-MOSFET remained constant at 6 cm2/Vs. For the resulting OpAmp with IMP, the common-mode input voltage range as well as the open loop gain was increased by 1.5 V and 4 dB compared to non-implanted devices. This improvement was observed across the entire analyzed temperature range from room temperature up to 350°C.

A −4–4 V Input Common-Mode Range Bidirectional Current Shunt Monitor

This study describes a novel bidirectional current shunt monitor (CSM) circuit operating at both positive and negative common-mode (CM) voltages. The proposed CSM circuit mainly consists of two comparators, three error amplifiers, several current-mirror transistors and a few resistors. One comparator is used to detect current flowing direction, and the other one is utilized to ensure good operation of CSM circuit with both positive and negative CM voltages. The proposed CSM circuit has been implemented in SMIC 0.18[Formula: see text][Formula: see text]m standard CMOS process and its performances have been verified by simulations. The simulated results show that the proposed CSM circuit, at a supply voltage of 5[Formula: see text]V and with an input CM voltage range from [Formula: see text] to 4[Formula: see text]V, can sense a voltage difference of 4–40[Formula: see text]mV and keep a constant scaled gain of 100[Formula: see text]V/V. The gain error is less than 0.65% and the common-mode rejection ratio (CMRR) is higher than 130[Formula: see text]dB at 1[Formula: see text]kHz. Simulation results show that the output voltage of CSM circuit varies linearly with the CSM input sense voltage.

A Low Power High Precision Trim-Less Envelope Detector for Fail-Safe Circuit in LVDS Receiver

This brief presents a trim-less precision envelope detector for fail-safe circuit in LVDS receiver. A preamp is proposed using ${g} _{m}$ -constant biasing concept to produce an accurate gain of 9.78 dB across PVT covering the full range of the LVDS input common-mode voltage. The preamp produces a fixed output common-mode voltage of 200 mV across supply voltage variation which reduces its complexity by alleviating the need of a trimming circuit. A unique reference voltage generation of the envelope detector based on level shifted output common-mode voltage accurately compares the output common-mode and negative peak voltages to set the detection threshold. An LVDS receiver adopting the proposed envelope detector was fabricated on a standard 0.13- ${\mu }\text{m}$ CMOS. With a supply voltage of 3.3 V, the envelope detector achieves a voltage trimming precision of 20 mV while only consuming 162 ${\boldsymbol{\mu }}\text{W}$ of power.

Compensation of self-heating-induced timing errors in bipolar comparators

Self-heating effects in bipolar comparators manifest themselves as signal-dependent output signal timing variation. In applications where comparator circuits are used for precise timing measurement of input signal threshold crossings, such as test and measurement instruments, self-heating presents a design challenge that must be addressed. A comparator circuit, utilizing a novel circuit-based self-heating compensation method, has been designed and fabricated in a BiCMOS HBT process. This self-heating compensation scheme differs from previously reported compensation circuitry in that it is designed for the compensation of asynchronous comparators. Measurements presented here demonstrate the effectiveness of the compensation circuitry at reducing self-heating-induced timing errors over a wide range of input signal amplitude and common-mode voltage.

An Ultra Low Voltage Low Power Self Biased Latched Comparator with Wide Input Common Mode Range for Biomedical Applications

This work describes an ultra low voltage, low power and self biased comparator with wide input common-mode range. The proposed comparator consists of a preamplifier followed by a regenerative back-to-back inverter latch, where two push pull NMOS and PMOS pairs are exploited to bias the preamplifier and adjust its output common mode voltage. This leads to a wide input common mode voltage range (from 0 V to 390 mV). Furthermore, the operation of proposed structure is relatively insensitive to process and temperature variations due to the push pull transistors, and low power consumption is achieved through sub-threshold region operation. The comparator circuit is designed using 65-nm CMOS technology with minimum supply voltage of 0.4 V. Simulation results show an average power consumption ranging from 141 nW to 188 nW for different input common mode voltage levels, where a simple power gating technique is employed to further reduce the power consumption. The Monte Carlo simulation shows an average offset of 450 μV with standard deviation of 3.3 mV. In addition, the comparator shows a kickback noise range of 0.3–2.4 mV (with input common mode range from 0 V to 390 mV) and input referred noise of 0.9 mV. The proposed comparator operates up to clock frequency of 1 MHz in most process corners and temperature range of 0–100°C which is suitable for most of the biomedical sensing applications.

Hardware Implementation of Overvoltage and Under voltage Protection

2,3 Abstract: The aim of the project is to make a low voltage and high voltage indicator. The system will save costly electrical and electronic appliances from the adverse effects of very high and very low mains voltages. A project has been proposed on simulating a overvoltage and under-voltage protector, with the hardware. The advantages of our project are -Wide single supply voltage range 2.0 V DC to 36 V DC ,Very low supply current drain (0.8mA) independent of supply voltage , low input biasing current 25mA.,Input common mode voltage range includes ground, differential input voltage range equal to the power supply voltage.

Digitally programmable low-voltage highly linear transconductor based on promising CMOS structure of differential difference current conveyor

A digitally programmable low-voltage highly linear transconductor (Gm stage) realization, using a promising CMOS structure of differential difference current conveyor (DDCC) and a R-2R ladder network, is introduced in this paper. Thanks to the efficiency of the DDCC CMOS structure, the transconductor exhibits excellent linearity in a wide range of the input voltage and its transconductance value is digitally programmable by the use of a R-2R ladder network. The CMOS structure of the DDCC is based on the latest bulk-driven quasi-floating-gate technique and hence it is capable to work under low-voltage power supply of ±0.5V and consumes 36μW of power. The differential input MOS transistor pairs of the proposed structure are simultaneously driven from bulk and quasi-floating-gate terminals; this leads to an increased value of the voltage gain, bandwidth, and input common-mode voltage range. The last one is the main benefit of this structure in comparison to already existing solutions. The proposed CMOS structure of the DDCC was designed and fabricated using 0.35μm CMOS AMIS process with total chip area 213μm×266μm. As an application example, a digitally programmable universal filter using three DDCCs and two grounded capacitors is presented.

A 0.7-V Opamp in Scaled Low-Standby-Power FinFET Technology

This paper demonstrates a FinFET operational amplifier (opamp), which is suitable to be integrated with digital circuits in a scaled low-standby-power (LSTP) technology and operates at extremely low voltage. The opamp is consisting of an adaptive threshold-voltage (Vt) differential pair and a low-voltage source follower using independent-double-gate- (IDG-) FinFETs. These two components enable the opamp to extend the common-mode voltage range (CMR) below the nominal Vt even if the supply voltage is less than 1.0V. The opamp was implemented by our FinFET technology co-integrating common-DG- (CDG-) and IDG-FinFETs. More than 40-dB DC gain and 1-MHz gain-bandwidth product in the 500-mV-wide input CMR at the supply voltage of 0.7V was estimated with SPICE simulation. The fabricated chip successfully demonstrated the 0.7-V operation with the 480-mV-wide CMR, even though the nominal Vt was 400mV.

Novel low-voltage low-power high-precision CCII± based on bulk-driven folded cascode OTA

This paper presents possible approaches to the design of a novel low-voltage, low-power, and high-precision current conveyor of the second generation (CCII±) based on the bulk-driven folded cascode operational transconductance amplifier (OTA) with extended input common-mode voltage range. This CCII± utilizes bulk-driven differential pairs to obtain a nearly rail-to-rail input stage at a low supply voltage. The proposed conveyor operates at a low supply voltage of ±400 mV with a reduced power consumption of only 64 μW. A current-mode multifunction filter is presented as an application of the CCII±. This filter provides five transfer functions simultaneously, namely low-pass, band-pass, high-pass, notch, and all-pass. The filter has the following properties and advantages: it employs three bulk-driven current conveyors BD-CCII±, three grounded resistors, and two grounded capacitors, which is suitable for integrated circuit implementation. Furthermore, the input signal is connected to the low-impedance X terminal of the BD-CCII± whereas the output signals are taken from the high-impedance output terminals Z+ and Z−. Finally, the pole frequency and quality factor of the designed filter are tunable independent of each other. PSpice simulation results using the 0.18 μm CMOS technology are included to prove the results.

A Laser-Trimmed Rail-to-Rail Precision CMOS Operational Amplifier

This brief presents a rail-to-rail input-output precision operational amplifier with integrated laser-trimmable polysilicon resistors for reducing the input offset voltage. The amplifier is fabricated in a standard Taiwan Semiconductor Manufacturing Company 0.18-μm complementary-metal-oxide-semiconductor process technology. The resistors' trimming sequence allows for minimizing the offset voltage over the complete input common mode voltage range (ICMR) extending from the ground to the supply. Experimental results are presented to demonstrate the steps involved in offset-voltage trimming. The prototype amplifier drives a 400-pF capacitive load and operates from a 3.3-V supply. The amplifier is unity-gain stable with a phase margin of 58° and has an open-loop direct-current gain greater than 130 dB with a unity-gain bandwidth of 0.5 MHz. Experimental results show that an untrimmed input offset voltage ranging from +0.1 to +0.5 mV over the ICMR was reduced to -30 to + 30 μV.

A Class AB Amplifier with a Reduced Crossover Distortion for Signal Driver

  Abstract—A high-driving class-AB buffer amplifier, which consists of a high-gain input stage and a pair of operational transconductance amplifier, is proposed. This paper presents a novel systematic offset minimization The high-driving capability is mainly provided by the folded amplifier class-AB CMOS operational amplifier. The proposed structure has a replica-gain circuit, generating a dc replica bias to the differential input stage, and providing differential gain as well as level conversion to drive the class- AB output stage .The circuit contains transconductance amplifiers in a rail to rail operation with both input and output stage based on the microwind technology and the offset due to device mismatch. An op amp low Cmos design is present in this paper. The circuit uses dual transconductance input pairs to achieve a rail-to-rail common mode input voltage range. Special attention has been given to the offset voltage cancellation of the op amps., and the circuit exhibits the settling time of 3 µs, for a voltage swing of 3.3 V under a 560pF capacitance load with a power supply of 5 V. The offset voltage of the amplifier reduced to a very small value of 0.0182mv.The area of this amplifier is 40*70 µm2.

A Current-Feedback Instrumentation Amplifier With 5 $\mu{\hbox{V}}$ Offset for Bidirectional High-Side Current-Sensing

This paper describes an instrumentation amplifier for bidirectional high-side current-sensing applications. It uses a multipath indirect current-feedback topology. To achieve low offset, the amplifier employs a combination of chopping and auto-zeroing in a low frequency path to cancel the offset of a wide-band amplifier in a high frequency path. With a 60 kHz chopper clock and a 30 kHz auto-zero clock, this offset-stabilization scheme results in an offset voltage of less than 5 muV , a CMRR of 143 dB and a common-mode input voltage range from 1.9 to 30 V. The input voltage-to-current (V-I) converters required by the current-feedback topology are implemented with composite transistors, whose transconductance is determined by laser-trimmed resistors. This results in a less than 0.1% gain inaccuracy. The instrumentation amplifier was realized in a 0.8 mum BiCMOS process with high voltage transistors, and has an effective chip area of 2.5 mm2 .

1-V Rail-to-Rail CMOS OpAmp With Improved Bulk-Driven Input Stage

This paper introduces a CMOS operational amplifier with rail-to-rail input and output voltage ranges, suitable for operation in extremely low-voltage environments. The approach is based on a bulk-driven input stage with extended input common-mode voltage range, in which the effective input transconductance is enhanced by means of a partial positive feedback loop. As a result, a gain and gain-bandwidth product performance similar to that of an amplifier using a gate-driven approach is obtained. Output rail-to-rail operation is achieved by means of a push-pull stage, which is biased in class-AB by using a static feedback loop, thus avoiding frequency limitations inherent in dynamic-feedback tuning schemes. The proposed two-stage operational amplifier was designed to operate with a 1-V supply, and a test chip prototype was fabricated in 0.35-mum standard CMOS technology. The experimental performance features an open-loop DC gain higher than 76 dB and a closed-loop unity-gain bandwidth above 8 MHz when a 1-MOmegapar17-pF load is connected to the amplifier output.

Transistor inversion level independent circuit technique for low-voltage rail-to-rail amplifiers

Rail-to-rail amplifiers are based on an input stage made up of two parallel-connected complementary differential pairs. The paper introduces a circuit technique for maintaining the small-signal behaviour (i.e. the transconductance, gm) of the amplifier constant over the entire input common-mode (CM) voltage range. The operation principle consists in comparing the total amplifier transconductance with a reference transconductance value and then generating an appropriate bias current for one of the two pairs of the rail-to-rail input stage. Thus, the technique is universal, since it is valid regardless of the gm/ID characteristic and the operating region of the input devices. Also, the accuracy in providing a constant transconductance does not depend on precise matching between n-channel and p-channel input transistors, which makes the technique robust. Experimental results from a 0.8-μm CMOS test chip demonstrate that amplifier transconductance variations, obtained as a function of the input CM voltage, are lower than for any previously reported technique.

Rail-to-rail constant- gm operational amplifier for video applications

This paper presents an operational amplifier (op-amp) with input/output rail-to-rail capability suitable for video applications. The input stage, which is based on two complementary differential pairs, provides a constant transconductance over the entire input common-mode voltage range, whereas a class-AB output stage with an accurate control of the quiescent current ensures rail-to-rail output swing even in the presence of a heavy load. Both the input stage transconductance and the output stage quiescent current are controlled by means of static loops, which allows high-frequency operation of the amplifier. In addition, the proposed constant-transconductance technique does not depend on the I– V characteristics of the input transistors—it is therefore compatible with modern submicron CMOS devices—and does not rely on any accurate matching between the complementary input pairs. The op-amp was designed to operate with 3 V of supply voltage and fabricated in 0.8-μm CMOS technology. The measured open-loop gain and unity gain-bandwidth for a 100-Ω∥100-pF load are 60 dB and 32 MHz, respectively, while the output swing with the same output load reaches 83% of the total supply voltage.

1-V quasi constant- gm input/output rail-to-rail CMOS op-amp

A CMOS operational amplifier with input/output rail-to-rail range is presented. The circuit operates with a 1-V single supply. It uses dynamically biased input level shifters, controlled by a novel tuning scheme, to extend the input common-mode voltage range from one rail to the other. The tuning circuit takes the total biasing current of the amplifier input stage and, hence, its small-signal response into account. As a result, the total input transconductance variations are lower than ±10% over the entire voltage range. Experimental results on a test-chip fabricated in standard 0.8-μm CMOS technology are given.

Constant-gm constant-slew-rate high-bandwidth low-voltage rail-to-rail cmos input stage for vlsi cell libraries

This paper introduces a general-purpose low-voltage rail-to-rail input stage suitable for analog and mixed-signal applications. The proposed circuit provides, simultaneously, constant small-signal and large-signal behaviors over the entire input common-mode voltage range, while imposing no appreciable constraint for high-frequency operation. In addition, the accuracy of the circuit does not rely on any strict matching of the devices, unlike most of the traditional approaches based on complementary input pairs, which need to compensate for the difference in mobility between electrons and holes with the transistor aspect ratios. Also, the technique is compatible with deep submicrometer CMOS devices, where the familiar voltage-to-current square law in saturation is not completely satisfied. Based on the proposed input stage, a transconductor with rail-to-rail input common-mode range and an input/output rail-to-rail operational amplifier were developed. Both cells were designed to operate with a 3-V single supply and fabricated in standard 0.8-μm CMOS technology. Experimental results are provided.

General purpose rail-to-rail input circuit with constant behaviour for VLSI cell libraries

A general purpose rail-to-rail input stage suitable for analogue and mixed signal applications and compatible with modern submicron CMOS technologies, is introduced. The circuit provides, simultaneously, a constant small- and large-signal behaviour over the entire input common-mode voltage range, whilst imposing no appreciable constraint for high-frequency operation. Experimental results are given.

Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input Stages

Two robust CMOS rail-to-rail OpAmp input stages are presented for low voltage (≤ 3 V) applications. The robust input stages are implemented using two recently reported universal approaches to achieve constant transconductance. Transconductance control circuit is also introduced to compensate for K_{p}, K_{n} mismatch of PMOS and NMOS differential pairs in the input stage. The input stages are designed for operation in the strong inversion and have a rail-to-rail common mode input voltage range. Compared with an OpAmp with simple complementary input pairs, a two stage rail-to-rail OpAmp design example exhibits lower total harmonic distortion (THD) levels over the entire common mode input voltage range.

Some Design Aspects of a Two-Stage Rail-to-Rail CMOS Op Amp

A two-stage low-voltage CMOS op amp with rail-to-rail input and output voltage ranges is presented. The circuit uses complementary differential input pairs to achieve the rail-to-rail common-mode input voltage range. The differential pairs operate in strong inversion, and the constant transconductance is obtained by keeping the sum of the square roots of the tail currents constant. Such an input stage has an offset voltage which depends on the common input voltage level, resulting in a poor common-mode rejection ratio. Therefore, special attention has been given to the reduction of the op amp’s systematic offset voltage. Gain-boost amplifiers are connected in a special way to provide not only an increase of the low-frequency open-loop gain, but also to provide a significant reduction of the systematic offset voltage.