Common-mode Feedforward Research Articles

A 0.3 V OTA with Enhanced CMRR and High Robustness to PVT Variations

In this paper, we present a 0.3 V body-driven operational transconductance amplifier (OTA) that exploits a biasing approach based on the use of a replica loop with gain. An auxiliary amplifier is exploited both in the current mirror load of the first stage of the OTA and in the replica loop in order to achieve super-diode behavior, resulting in low mirror gain error, which enhances CMRR, and robust biasing. Common-mode feedforward, provided by the replica loop, further enhances CMRR. Simulations in a 180 nm CMOS technology show 65 dB gain with 2 kHz unity-gain frequency on a 200 pF load when consuming 9 nW. Very high linearity with a 0.24% THD at 90% full-scale and robustness to PVT variations are also achieved.

A 0.6-V pseudo-differential OTA with switched-opamp technique for low power applications

A low-voltage, pseudo-differential OTA is presented in this study for power-effective applications. The cross-coupled common-mode feedforward (CMFF) technique is proposed to improve the CMRR performance and double transconductance of pseudo-differential OTA with the same power consumption as the conventional one. Implemented under the supply voltage of 0.6 V, the designed OTA, which converts the single-ended signal into the fully differential signal, is used as the input buffer of ADC. Considering the particularity of ADC application, switched-opamp (SO) technology is designed to turn off amplifier partly for compromising high power efficiency and short start time. Implemented in the 0.18-μm standard CMOS process, the OTA occupies an active chip area of 0.05 mm2 and provides the settling time of 310 ns with 0.1% accuracy for 0.6 Vpp output step. The measured input noise spectrum density is −147 dBv/Hz (45 nv/Hz) @ 25 MHz. The output-referred integrated noise voltage is 485 μV from 20 Hz to 25 MHz.

2‐1 Switched‐current multi‐stage noise‐shaping delta–sigma modulator with a digital noise‐cancellation circuit

This study focuses on the design of a 2-1 switched-current (SI) multi-stage noise-shaping delta–sigma modulator with a digital noise-cancellation circuit. The noise-cancellation circuit is designed by employing various algorithms for designing the logic circuits and constructing a delay block with an inverter and a transmission gate. It can eliminate the higher-order quantisation noise from the first stage of the modulator completely. In the proposed differential current-mode sample-and-hold circuit, low-input impedance is presented with feedback and width-length adjustment in SI feedback memory cell, a coupled differential replicate with the common-mode feed-forward (CMFF) circuit is used to stabilise the common-mode bias voltage at input terminal, and a differential cross-connected CMFF circuit is utilised to fix the bias voltages. Post-layout simulations reveal that the simulated signal-to-noise-and-distortion ratio (SNDR) was 90.4 dB and the effective number of bit (ENOB) was 14.73 bits. Measurements show that the SNDR was 59.13 dB and the ENOB was 9.53 bits at a sampling rate of 10.24 MHz, an oversampling ratio of 256, and a signal bandwidth of 20 kHz. This design has a power requirement of 12.99 mW from a supply voltage of 1.8 V and occupies a core area of 0.14 mm2.

A Novel Fully Differential Second Generation Current Conveyor and Its Application as a Very High CMRR Instrumentation Amplifier

This paper aims to introduce a novel Fully Differential second generation Current Conveyor (FDCCII) and its application to design a novel Low Power (LP), very high CMRR, and wide bandwidth (BW) Current Mode Instrumentation Amplifier (CMIA). In the proposed application, CMRR, as the most important feature, has been greatly improved by using both common mode feed forward (CMFF) and common mode feedback (CMFB) techniques, which are verified by a perfect circuit analysis. As another unique quality, it neither needs well-matched active blocks nor matched resistors but inherently improves CMRR, BW, and power consumption hence gains an excellent matchless choice for integration. The FDCCII has been designed using 0.18 um TSMC CMOS Technology with ±1.2 V supply voltages. The simulation of the proposed FDCCII and CMIA have been done in HSPICE LEVEL 49. Simulation results for the proposed CMIA are as follow: Voltage CMRR of 216 dB, voltage CMRR BW of 300 Hz. Intrinsic resistance of X-terminals is only 45 Ω and the power dissipation is 383.4 μW. Most favourably, it shows a constant differential voltage gain BW of 18.1 MHz for variable gains (here ranging from 0 dB to 45.7 dB for example) removing the bottleneck of constant gain-BW product of Voltage mode circuits.

Analysis and design of highly linear triode‐mode based OTA and its application to a wide tunable Gm‐C filter

SummaryIn this paper, a new highly linear operational transconductance amplifier (OTA) based on triode‐mode input transistors is introduced. An analysis based on theoretical relations and simulation results is presented that aims to obtain the best operating points of triode‐mode and cascode transistors to achieve the highest linearity. The proposed analysis is utilized to design a linear pseudo‐differential OTA, benefiting a linear common mode feedforward and an appropriate common mode feedback circuit. The common mode feedforward circuit is also regulated in the same manner as main the transconductor to stabilize the output common mode voltage during tuning action and achieve higher common mode rejection ratio. Proposed OTA is used to implement a tunable low‐power linear Gm‐C filter. The cutoff frequency of the filter is tunable from 2.7 to 44 MHz while its power consumption changes from 3.5 to 8.5 mW in the entire tuning range. By applying input voltages up to 1.1 Vp‐p, the filter's IM3 remains less than −48 dB for various cutoff frequencies. The proposed OTA and filter are simulated in 0.18‐μm CMOS technology with Hspice simulator. Copyright © 2017 John Wiley & Sons, Ltd.

High speed switched-current memory cell with very low offset and charge injection errors

In this paper a high speed class AB switched-current memory cell is presented. Memory transistors have been designed in triode region in order to reduce the threshold voltage mismatch and clock feed-through errors. Also a modified Flipped Voltage Follower (FVF) circuit is used to cancel charge injection error. Besides, this cell consists of a new common-mode feedforward (CMFF) circuit which attenuates the common mode components and improves offset error at output. Furthermore, a coupled differential (CDR) memory cell (MC) is used to eliminate the clock feedthrough (CFT) error considerably. All of the presented circuits have been designed by using TSMC 0.18μm process parameters and simulated in HSPICE. Simulation results show that maximums of THD, SNR and SFDR at clock frequency of 100MHz and 1MHz as input frequency are –71dB, 71.2dB and 68dB respectively. Obtained results demonstrated considerable improvement in the circuit performance which confirm the excellence of proposed memory cell in comparisons to previous cells.

A Wearable 8-Channel Active-Electrode EEG/ETI Acquisition System for Body Area Networks

This paper describes an 8-channel gel-free EEG/electrode-tissue impedance (ETI) acquisition system, consisting of nine active electrodes (AEs) and one back-end (BE) analog signal processor. The AEs amplify the weak EEG signals, while their low output impedance suppresses cable-motion artifacts and 50/60 Hz mains interference. A common-mode feed-forward (CMFF) scheme boosts the CMRR of the AE pairs by 25 dB. The BE post-processes and digitizes the analog outputs of the AEs, it also can configure them via a single-wire pulse width modulation (PWM) protocol. Together, the AEs and BE are capable of recording 8-channel EEG and ETI signals. With EEG recording enabled, ETIs of up to 60 kΩ can be measured, which increases to 550 kΩ when EEG recording is disabled. Each EEG channel has a 1.2 GΩ input impedance (at 20 Hz), 1.75 μVrms (0.5-100 Hz) input-referred noise, 84 dB CMRR and ±250 mV electrode offset rejection capability. The EEG acquisition system was implemented in a standard 0.18 μm CMOS process, and dissipates less than 700 μW from a 1.8 V supply.

1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS

This paper describes the front-end of a fully integrated analog interface for 300 MSps, high-definition video digitizers in a system on-chip environment. The analog interface is implemented in a 1.2 V, 65-nm digital CMOS process and the design minimizes the number of power domains using core transistors only. Each analog video receiver channel contains an integrated multiplexer with a current-mode dc-clamp, a programmable gain amplifier (PGA) and a pseudo second-order RC low-pass filter. The digital charge-pump clamp is integrated with low-voltage bootstrapped tee-switches inside the multiplexer, while restoring the dc component of ac-coupled inputs. The PGA contains a four-stage fully symmetric pseudo-differential amplifier with common-mode feedforward and inherent common-mode feedback, utilized in a closed loop capacitive feedback configuration. The amplifier features offset cancellation during the horizontal blanking. The video interface is evaluated using a unique test signal over a range of video formats for INL+/DNL+, INL-/DNL-. The 0.07-0.39 mV INL, 2-70 μV DNL, and 66-74 dB of SFDR, enable us to target various formats for 9-12 bit Low-voltage digitizers.

A 250 MHz low voltage low-pass Gm-C filter

A high speed and high linearity Gm-C low-pass filter is presented. The proposed OTA is designed under low power supply voltage consideration while its gain, excess phase, and linearity are well maintained. The common-mode control system, including common-mode feedback and common-mode feedforward circuits, is added to ensure stability of the proposed filter. Measurement results show that the inter-modulation distortion of ?40 dB can be achieved with 250 MHz 400 mVpp balanced differential input signals. The filter works in 1 ? V supply voltage and its power consumption is 32 mW.

A 1 GHz Equiripple Low-Pass Filter With a High-Speed Automatic Tuning Scheme

A continuous-time fourth-order equiripple linear phase <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Gm</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined common-mode feedforward and common-mode feedback circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining an equivalent negative resistor circuit at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the deep-NWELL technology. The modified automatic tuning circuit relaxes the speed requirement of the tuning blocks. Through the use of the operational transconductance amplifier as a building block with the automatic tuning scheme, the filter - 3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The - 43 dB of IM3 at filter cutoff frequency is obtained with -4 dbm two-tone signals. Implemented in 0.18-μ m CMOS process, the chip occupies 1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 175 mW at a 1.5-V supply voltage.

CMFF CMOS 인버터 타입 OTA를 이용한 Gm-C 필터 설계

In this paper, a Gm-C LPF utilizing common-mode feedforward (CMFF) CMOS inverter type operational transconductance amplifier (OTA) has been designed and verified by circuit simulations. The CMFF CMOS inverter OTA was optimized for wide input linearity and low current consumption using a standard 0.18 <TEX>${\mu}m$</TEX> CMOS process; gm of 100 <TEX>${\mu}S$</TEX> and current of 100 <TEX>${\mu}A$</TEX> at supplied voltage of 1.3 V. Using this optimized CMFF CMOS inverter type OTA, an elliptic 5th order Gm-C LPF for GPS specifications was designed. Gain and frequency tuning of the LPF was done by changing the internal supply voltages. The designed Gm-C LPF gave pass-band ripple of 1.6 dB, stop-band attenuation of 60.8 dB, current consumption of 0.60 mA at supply voltage of 1.2 V. The gain and frequency characteristics of designed Gm-C LPF was unchanged even though the input common-mode voltage is varied.

Selection of the common-mode feedback network connection of fully differential Gm-C filters

It is well known that fully differential (FD) structures have many advantages over their single-ended counterparts. However, the main disadvantage of FD circuit is the potential instability caused by the inherent common-mode (CM) positive feedback loop. To solve such an instability problem, extra common-mode feedback (CMFB) and/or common-mode feedforward (CMFF) circuitries are often incorporated to stabilise the circuits. We present a systematic method for checking the stability condition and identifying the most suitable CMFB network connection for a particular FD Gm-C filter. It has been demonstrated that the CMFB network connection that provides highest CM rejection is not necessarily the conventional arrangement commonly used in FD Gm-C design.

1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters

This paper describes 10-bit, 80-MSample/s pipelined A/D converters for wireless-communication terminals. To reduce power consumption, we employed the I/Q amplifier sharing technique [1] in which an amplifier is used for both I and Q channels. In addition, common-source, pseudo-differential (PD) amplifiers are used in all the conversion stages for further power reduction. Common-mode disturbances are removed by the proposed common-mode feedforward (CMFF) technique without using fully differential (FD) amplifiers. The converter was implemented in a 90-nm CMOS technology, and it consumes only 24 mW/ch from a 1.2-V power supply. The measured SNR and SNDR are 58.6 dB and 52.2 dB, respectively.

A Novel CMOS OTA Based on Body-Driven MOSFETs and its Applications in OTA-C Filters

The operational transconductance amplifier (OTA) is one of the most significant building-blocks in integrated continuous-time filters. Traditional OTAs suffer linearity reduction as a result of the MOSFET scaling trend. In this paper, a body-driven (BD) CMOS triode-based fully balanced OTA is proposed to achieve low distortion and linear frequency tuning. In contrast to the gate-driven based OTAs (that have the tradeoff of input and tuning range), BD-based OTAs operate under a wide input range over a large tuning interval. Common-mode (CM) feedforward and CM feedback schemes have been developed so that the CM voltage varies only 7 mV over a tuning range of 1.2 V = Vtune = 1.58 V. Using the 0.18-mum N-well CMOS process, a third-order elliptic low-pass filter is implemented with the aid of the proposed OTA. The total harmonic distortion ( is -45 dB for 0.8-V peak-peak (Vpp) fully differential input signals. A dynamic range of 45 dB is obtained with the OTA's noise integrated over 1 MHz.

A 270 MHz, 1 Vpk-pk, Low-Distortion Variable Gain Amplifier in a 0.35 μm CMOS Process

A fully balanced CMOS Variable Gain Amplifier (VGA) for high frequency applications and large signals is presented. The VGA consists of an analog multiplier, current gain stages, and resistive loads. A frequency compensation scheme based on a capacitive feed-forward technique increases the bandwidth by more than 60 %. Common-Mode Feed-Forward (CMFF) techniques are used to minimize dc offsets. The gain can be programmed from 0 dB to 42 dB with -3 dB bandwidth greater than 270 MHz. The Third Harmonic Distortion (HD3) is less than -55 dB for differential input and output voltages of 1 V pk-pk . The VGA was fabricated in 0.35 µm CMOS process, and consumes around 54 mW from a single power supply of 2.7 V.

Nonlinear effects in pseudo differential OTAs with CMFB

A general description of nonlinearities in pseudo differential operational transconductance amplifiers (OTA) with common-mode feedback (CMFB) is introduced. The effects of CMFB nonlinearities on the differential signals are evaluated and design tradeoffs including nonidealities are determined. A practical pseudo differential fully balanced fully symmetric OTA architecture with common-mode feedforward (CMFF) is used as a case study to probe the theory. The OTA has an inherent common-mode detector; hence, the CMFB circuit is efficiently implemented. The OTA is used to implement a 100-MHz fourth-order linear-phase OTA-C filter.

A 2-v/sub pp/ 80-200-mhz fourth-order continuous-time linear phase filter with automatic frequency tuning

A CMOS 80-200-MHz fourth-order continuous-time 0.05° equiripple linear phase filter with an automatic frequency tuning system is presented. An operational transconductance amplifier based on transistors operating in triode region is used and a circuit that combines common-mode feedback, common-mode feedforward, and adaptive bias is introduced. The chip was fabricated in a 0.35-μm process; filter experimental results have shown a total harmonic distortion less than -44 dB for a 2-V/sub pp/ differential input with a single 2.3-V power supply. The group delay ripple is less than 4% for frequencies up to 1.5 f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> . The frequency tuning error is below 5%.

A pseudo differential complex filter for bluetooth with frequency tuning

A 12th-order OTA-C complex filter with a nonconventional frequency tuning for a Bluetooth receiver is implemented in a low-cost mainstream 0.35-/spl mu/m CMOS process. This proposed frequency tuning scheme is simpler than the conventional one based on phased-locked loop (PLL). Furthermore, a high-speed pseudo differential OTA using common-mode feedforward (CMFF) and common-mode feedback (CMFB) strategy is proposed. The filter bandwidth is 1 MHz and is centered at 2 MHz. Image and adjacent channels are attenuated by more than 45 and 27 dB, respectively. The integrated input referred noise is 29 /spl mu/V/sub rms/, and the filter chip dissipates 4.7 mA from a 2.7 V supply. The theoretical and experimental results are in good agreement.

A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector

A pseudo-differential fully balanced fully symmetric CMOS operational transconductance amplifier (OTA) architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. The OTA achieves a third harmonic distortion of -43 dB for 900 mV/sub pp/ at 30 MHz. The OTA, fabricated in 0.5-μm CMOS process, is used to design a 100-MHz fourth-order linear phase filter. The measured filter's group delay ripple is 3% for frequencies up to 100 MHz, and the measured dynamic range is 45 dB for a total harmonic distortion of -46 dB. The filter consumes 42.9 mW per complex pole pair while operating from a ±1.65-V power supply.

An enhanced adaptive Q-tuning scheme for a 100-MHz fully symmetric OTA-based bandpass filter

A tuning scheme for continuous-time high-Q biquad filters is presented. An improvement over the existing implementation of the modified-LMS Q-tuning scheme is proposed and efficiently combined with the frequency tuning based on phase-locked loops. The proposed scheme takes much less area without compromising the accuracy achieved previously. The proposed unified Q- and f/sub 0/-tuning scheme does not require the Q-tuning loop to be slower than the f/sub 0/-tuning loop. The optimal case is to have equal speeds for both loops. Also, a low-voltage pseudo-differential operational transconductance amplifier with inherent common-mode feedforward is introduced. The structure is fully symmetric and suitable for high-frequency applications. An experimental test chip is fabricated in standard CMOS 0.5-μm technology, with a bandpass filter of center frequency 100 MHz and Q of 20, along with the proposed tuning scheme. The measured Q-tuning error is around 1%. Expected and experimental results are in good agreement.