Common-mode Current Reduction Research Articles

In depth study of two solutions for common mode current reduction in six-phase machine drive inverters

In depth study of two solutions for common mode current reduction in six-phase machine drive inverters

A Limited Common-Mode Current Switched-Capacitor Multilevel Inverter Topology and Its Performance and Lifetime Evaluation in Grid-Connected Photovoltaic Applications

In this paper, a switched-capacitor multilevel inverter with voltage boosting and common-mode-voltage reduction capabilities is put forth. The proposed inverter is synthesized with one-half bridge and several switched-capacitor cells. Due to the voltage boosting and common-mode current reduction features, the proposed multilevel inverter is suitable for grid-connected PV applications. In addition, an analytical lifetime evaluation based on mission profile of the proposed inverter has been presented to derive lifetime distribution of semiconductors. Whereas in the proposed inverter, any components failure can bring the whole system to a shutdown. The series reliability model is used to estimate the lifetime of the overall system. The performance of the suggested multilevel inverter in grid-connected applications is verified through the simulation results using the grid-tied model in Matlab/Simulink. Moreover, the viability and feasibility of the presented inverter are proven by using a one kW lab-scaled prototype.

Optimized Filter Design for Common-Mode Current Reduction in Four-Wire Inverter-Fed Motors

Two optimized filter topologies for four-wire electric drive systems (EDSs) are proposed with smaller size, lower power loss, and larger common-mode (CM) current reduction than the usual filter topologies. It has been previously shown that using a four-wire topology reduces the CM current in a wide frequency range, when compared with the three-wire one. However, there still exist low- and high-frequency resonances in the transfer function between neutral and inverter output voltage, resulting in the increase of CM current. By means of the transfer function analysis, two types of optimized filter topology specified for the four-wire EDS are proposed. Unlike conventional CM filter (CMMF), the design of these two new filters also requires a serious consideration of the characteristics of motor and cable impedance. Based on the design procedure, these two filters are built with excellent performance of CM current reduction in the whole frequency range. Besides, compared with conventional CMMF used for three-wire EDS, they also show benefits, such as lower power loss and less implementation space. All theoretical analyses are validated by the experimental measurements and can benefit further studies.

Characterization of Low-Inductance SiC Module With Integrated Capacitors for Aircraft Applications Requiring Low Losses and Low EMI Issues

Future aircrafts will be composed of high number of power converters having always higher power density and efficiency. In order to increase performance of such converters, a good option is the use of silicon carbide (SiC) transistors. Although these components reduce losses when compared to their silicon-based counterpart, they increase switching speed and overshoot during commutation, which can cause serious electromagnetic interference issues and overvoltages on loads connected to these converters. For that reason, power modules containing SiC transistors must have the lowest possible parasitic inductance. This article presents a multilevel low-inductance SiC power module designed to optimize a three-phase 540 V/15 kVA inverter for modern aircrafts. Precise dynamic characterization is performed in order to accurately determine switching energies and to show improvement of loss performance of this power module when compared to discrete components and also to power modules from the market. Inverter input and output common mode current reduction due to integrated common mode capacitors in the power module is experimentally shown.

Common-Mode Current Reduction at DC and AC Sides in Inverter Systems by Passive Cancellation

It is well known that PWM inverters generate common-mode (CM) voltages, which may cause the CM electromagnetic interference and leakage current in the applications such as photovoltaic or motor drive systems. The CM noise issue becomes more severe with the application of silicon-carbide devices, which have higher dv/dt than silicon devices. In this article, a passive cancellation method is proposed by inserting two CM transformers (CMT) into the input and output side of the inverter, respectively. The selection of the turns ratio for two CMTs is analyzed and revealed to achieve the best CM noise cancellation, and the influence of the parasitics in the CMT is investigated as they limit the bandwidth for CM noise cancellation. Compared to the passive filter, floating filter, and the active cancellation method, the proposed method could reduce the CM noise at both sides simultaneously regardless of the CM impedance of the source or the load. A single-phase inverter is built, and the proposed method achieves 40 dB reduction at both sides, which verifies the effectiveness of the proposed method.

Common-Mode Current Reduction with Synchronized PWM Strategy in Two-Inverter Air-Conditioning Systems

Common-Mode Current Reduction with Synchronized PWM Strategy in Two-Inverter Air-Conditioning Systems

A New Modulation Strategy to Reduce Common-Mode Current of Indirect Matrix Converter

This letter presents a new space vector modulation strategy adopting new zero vectors to achieve common-mode current (CMC) reduction for indirect matrix converter (IMC). By substituting conventional zero vectors by new zero vectors, the impedance of common-mode loop increases, which contributes to CMC reduction. Thus, the IMC system with the proposed method alleviates the adverse effects of CMC for ac drives. Moreover, additional hardware and complex commutation process are not required. Experiments are conducted to verify the effectiveness of the proposed method.

Validation of Prediction Method of Common-Mode Current Reduction Based on Imbalance Difference Model for Differential Transmission Line Placed Near Edge of Adjacent Ground Plane

Validation of Prediction Method of Common-Mode Current Reduction Based on Imbalance Difference Model for Differential Transmission Line Placed Near Edge of Adjacent Ground Plane

SVM Strategies for Common-Mode Current Reduction in Transformerless Current-Source Drives at Low Modulation Index

In transformerless high-power pulse width modulation (PWM) current-source drives, common-mode inductor is implemented to attenuate the common-mode voltage (CMV). However, the common-mode inductor is bulky and costly, so that scaling down the size of the common-mode inductor can achieve the system size reduction and efficiency enhancement. The size of the common-mode inductor is mainly related to the maximum common-mode current, which occurs at the resonant frequency of the common-mode circuit when motor speed is low. Previous research demonstrates that 3-segment average-value-reduction (AVR) space vector modulation (SVM) has good common-mode resonance suppression performance by attenuating the third-order CMV from the inverter. However, as studied in this paper, when modulation index of the inverter is lower than 0.4, the performance of 3-segment AVR SVM is affected as the dwell time of zero vector becomes too long to effectively compensate the CMV introduced by the active vectors. To overcome this problem, three modified AVR SVM schemes are proposed in this paper, where the single long zero vector is separated into two segments in the PWM sequence. The working principles, CMV reduction performance, harmonic performance, and switching frequency analysis of the proposed SVM methods are presented in detailed. Experiments are conducted to verify the effectiveness of the proposed methods.

Reduction of Common Mode Currents Generated by Three-Level Inverters with Consideration of Motor Overvoltages

In adjustable speed drive applications, the switching of the inverter semiconductors generates common mode currents as well as harmful overvoltages on the motor terminals when long cables are used. Consequently, bulky and expensive input and output filters must be used. This work aims at reducing these disturbances from their origin by using a three-level neutral-point-clamped (NPC) inverter controlled with a new pulse-width-modulation (PWM) strategy. Whereas previous common mode noise-reducing strategies usually generate higher overvoltages than conventional ones, the proposed PWM is able to manage both problems thanks to its internal degrees of freedom.

Implantation par porteuses d'une stratégie MLI réduisant les courants de mode commun générés par un onduleur NPC

This paper presents a new pulse-width-modulation strategy for the reduction of common-mode currents in adustable-speed-drive applications using a three-level neutral pointclamped inverter. It is implemented through a saw-tooth carrier-based modulator which makes it possible to control the degrees of freedom provided by the strategy.

Reduction of common-mode currents in PWM inverter motor drives

Reduction of common-mode currents in PWM inverter motor drives