Common-gate Transimpedance Amplifier Research Articles

Feedforward common gate transimpedance amplifier circuit based on CMOS active inductor in parallel

Feedforward common gate transimpedance amplifier circuit based on CMOS active inductor in parallel

Low-Power Organic Light Sensor Array Based on Active-Matrix Common-Gate Transimpedance Amplifier on Foil for Imaging Applications

This article presents a 57.6- $\mu \text{W}$ mechanically flexible active-matrix imaging system based on a $4\times 5$ array of light sensors, each composed of a photodetector (PD) using a light-sensitive organic polymer and a transimpedance amplifier (TIA) based on organic thin-film transistors and integrated thin-film carbon resistors. The PDs and the electronics are fabricated on separate plastic films and integrated into a system. Two different topologies for the TIA are designed, implemented, and characterized. The first topology is a self-biased TIA based on a gain-boosted operational amplifier (op-amp), providing an open-loop dc gain of 41.3 dB. This op-amp-based TIA, with a feedback resistor, provides stable current-to-voltage conversion (0–100 $\mu \text{A}$ and 2.0–3.7 V) at frequencies up to 300 Hz. The second topology is a low-power gain-boosted common-gate (GB CG) TIA that performs current-to-voltage conversion with a nonlinearity as small as ±0.3% within a bandwidth of 1 kHz. The output voltages of the light sensors are read and converted into a $4\times 5$ pixel gray-scale image displayed on a computer monitor to visualize the functionality of the system.

A Four-Phase Passive Mixer-First Receiver With a Low-Power Complementary Common-Gate TIA

This paper presents a four-phase passive mixer-first receiver using a common-gate (CG) trans-impedance amplifier (TIA), instead of a conventional shunt-feedback amplifier. The four-transistor TIA used in this work combines current-reuse with cross-coupled $g_{m}$ -boosting to achieve a reduced noise figure (NF) at low power levels. Moreover, complementary derivative-superposition (CDS) linearization within the TIA helps to improve the linearity with no additional power overhead. A prototype receiver is implemented in a 180 nm CMOS technology. The receiver operates from 0.3 to 1.3 GHz with a conversion gain of 21.9 dB. In measurements, the receiver achieved a noise figure of 5.8 dB and an in-band (IB) IIP3 of +7.2 dBm while consuming 0.34 mW power per TIA at 1 GHz. The measured spurious-free dynamic range (SFDR) at 1 GHz is 76.9 dB.

A Low-Voltage and Label-Free Impedance-Based Miniaturized CMOS Biosensor for DNA Detection

This study designs a low-voltage, label-free and fully integrated impedance-based biosensor using standard complementary metal oxide semiconductor (CMOS) technology to compute both capacitance and resistance of the electrode-electrolyte interface. The proposed biosensor circuit is composed of a common-gate transimpedance amplifier (CG-TIA) with two quadrature phase Gilbert cell double-balanced mixers and finally integrated with microelectrode using 0.18 µm Silterra CMOS technology process. The output value of the readout circuit was used to estimate the magnitude and phase of the measured admittance. The developed CG-TIA can achieve a gain of 88.6 dB up to a frequency of 50 MHz. The overall dynamic range was approximately 116 dB.

Regulated Common-Gate Transimpedance Amplifier Designed to Operate With a Silicon Photo-Multiplier at the Input

A transimpedance amplifier (TIA) in the front-end of a radiation detector is required to convert the current pulse produced by a light-detector to a voltage pulse with amplitude and shape suitable for the subsequent processing. We consider in this paper the specifications of a positron emission tomography (PET) scanner for medical imaging. The conventional approach is to use an avalanche photo-diode (APD) as the light-detector and a feedback TIA. We point out here that, when the APD is replaced by the more recent silicon photomultiplier (SiPM), a feedback TIA is not suitable, and we propose the use of a regulated common-gate (RC-G) TIA. We derive the transimpedance function of the RC-G TIA considering the parasitic capacitances that have a dominant effect on the pulse shaping. We use the result obtained to establish TIA design guidelines, and we show that these should be different with an APD and with a SiPM at the input. We identify the dominant noise source in the RC-G TIA, and we derive a closed form equation for the output noise rms voltage. A prototype TIA was designed for UMC 130 nm CMOS technology. We present simulation and experimental results that confirm that the RC-G circuit is suitable for implementation of the TIAs in the front-end of a PET scanner using SiPMs at the input.

Noise Performance of a Regulated Cascode Transimpedance Amplifier for Radiation Detectors

A low noise transimpedance amplifier (TIA) is used in radiation detectors to transform the current pulse produced by a photo-sensitive device into an output voltage pulse with a specified amplitude and shape. We consider here the specifications of a PET (positron emission tomography) system. We review the traditional approach, feedback TIA, using an operational amplifier with feedback, and we investigate two alternative circuits: the common-gate TIA, and the regulated cascode TIA. We derive the transimpedance function (the poles of which determine the pulse shaping); we identify the transistor in each circuit that has the dominant noise source, and we obtain closed-form equations for the rms output noise voltage. We find that the common-gate TIA has high noise, but the regulated cascode TIA has the same dominant noise contribution as the feedback TIA, if the same maximum transconductance value is considered. A circuit prototype of a regulated cascode TIA is designed in a 0.35 μm CMOS technology, to validate the theoretical results by simulation and by measurement.

Current-mode analogue interface for high-speed low-current differential signalling

In this work, we propose high-speed low-current differential signalling (LCDS) over an electrical chip-to-chip interconnect by using a common-gate transimpedance amplifier followed by a common-source TIA stage. LCDS uses a current-mode receiver compared to a conventional voltage-mode receiver used in most of the signalling technologies such as low-voltage differential signalling, voltage-mode signalling and current-mode logic. The minimum detectable signal level possible with a current-mode receiver for the targeted bit-error rate (BER) makes LCDS an attractive choice. Also the input impedance of the LCDS receiver can be made equal to 100 Ω differential for matching the characteristic impedance of electrical chip-to-chip interconnect. The complete design, analysis and noise characterisation of the TIA front-end is presented. The CGCSTIA is implemented in 1.8 V, 0.18 μm digital CMOS technology. The input-referred noise current and 3-dB bandwidth of the receiver are 1.57 μA and 5.75 GHz, respectively. For the targeted BER of 10−12, a data transfer rate of 6 Gb/s is achieved, while transmitting the data over a FR4 PCB trace of length 20 cm. The power dissipated in the current-mode receiver is 3.6 mW.

A 20-Gb/s Transformer-Based Current-Mode Optical Receiver in 0.13- $\mu\hbox{m}$ CMOS

A 20-Gb/s current-mode optical receiver is realized in a 0.13-μm CMOS process, which consists of a common-gate transimpedance amplifier (TIA) with on-chip transformers, a six-stage postamplifier (PA) with an offset cancellation network, and an output buffer. The transformer-based inductive peaking technique is exploited in the TIA to isolate the parasitic capacitances at high-impedance nodes and, hence, to enlarge the bandwidth. The PA incorporates source degeneration and interleaving active feedback techniques to achieve wide bandwidth and flat frequency response so as not to degrade the operation speed of the whole optical receiver. Measured results demonstrate 60-dbΩ transimpedance gain, 12.6-GHz bandwidth even with 0.4-pF large input parasitic capacitance, ߝ13-dBm sensitivity for a 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> bit error rate, and 38.3-mW power consumption from a single 1.2-V supply.

Low-noise differential transimpedance amplifier structure based on capacitor cross-coupled gm-boosting scheme

This paper presents a capacitor cross-coupled gm-boosting scheme for differential implementation of common-gate transimpedance amplifier (CG-TIA). A differential transimpedance amplifiers (DTIA) is designed by this scheme using two modified floating-biased CG stage with improved low corner frequency. Despite conventional methods for single-ended to differential conversion that increase the power and the noise for the same gain, the new DTIA gives a higher gain and hence reduces the input-referred noise power. Design of the DTIA circuit using 0.13μm CMOS technology illustrates near 1.7dB improvement in the circuit sensitivity and 5.2dB enhancement in transimpedance gain compared to its single-ended counterpart. Operation at very low frequencies and stable dc coupling to photodiode are other features of the proposed DTIA.

Gm-boosted differential transimpedance amplifier architecture

A modified floating biased common-gate transimpedance amplifier with improved low corner frequency is introduced. It is also shown that gm-boosting technique can be utilized for differential implementation of this transimpedance amplifier, without degrading the circuit sensitivity or using any off-chip components. HSPICE simulations for differential implementation illustrate more than two orders of magnitudes improvement of low corner frequency, about 80% increase in gain, and 20% reduction in input referred noise, compared to those of conventional single-ended floating biased common gate transimpedance amplifier.

1.25-Gb/s Regulated Cascode CMOS Transimpedance Amplifier for Gigabit Ethernet Applications

A transimpedance amplifier (TIA) has been realized in a 0.6-/spl mu/m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. Test chips were electrically measured on a FR-4 PC board, demonstrating transimpedance gain of 58 dB/spl Omega/ and -3-dB bandwidth of 950 MHz for 0.5-pF photodiode capacitance. Even with 1-pF photodiode capacitance, the measured bandwidth exhibits only 90-MHz difference, confirming the mechanism of the RGC configuration. In addition, the noise measurements show average noise current spectral density of 6.3 pA//spl radic/(Hz) and sensitivity of -20-dBm for a bit-error rate of 10/sup -12/. The chip core dissipates 85 mW from a single 5-V supply.

Wideband low noise CMOS transimpedance amplifier for gigaHertz operation

A novel low noise CMOS common gate transimpedance amplifier is presented. Simulated performances gives a 1.2 GHz bandwidth, 1.6 kΩ transimpedance gain, and very low input referred current noise. Results are comparable to those of a recent common base BiCMOS transimpedance amplifier.