Commercial Design Tools Research Articles

Full-Custom 90 nm CNTFET Process Design Kit: Characterization, Modeling, and Implementation

As the semiconductor industry enters the post-Moore era, the carbon nanotube field-effect transistor (CNTFET) has become a powerful substitute for silicon-based transistors beyond 5 nm process nodes due to its high mobility, low power consumption, and ultra-thin-body electrical advantages. Carbon-based transistor technology has made significant progress in device manufacture and preparation, but carbon-based process design kits (PDKs) that meet the standards of commercial design tools are still an important bottleneck hindering the development of carbon-based integrated circuits. For the first time, a complete full-custom 90 nm CNTFET PDK is proposed in this paper, which includes Pcells for transistors, resistors, and capacitors; a compact model; DRC/LVS/PEX rules; and a standard cell and timing library. It can support the entire design flow of analog, digital, and mixed-signal carbon-based integrated circuits. To achieve an accurate compact model, the back-gate effect of CNTFETs and the influence of gate/drain voltage on transport probability are analyzed. Then the theoretical formulas for mobility and channel current are established. The comparison of the simulation and test results of CNTFET characteristics proves the accuracy of the compact model. Using this PDK, combined with standard IC design tools and design flow, the circuit and layout of an operational amplifier, SRAM, and 8-bit counter are completed. The simulation results verify the correctness and effectiveness of the PDK, laying a solid foundation for the large-scale industrialization of carbon-based integrated circuits.

CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning Strategies

The design automation community has been actively exploring machine learning for VLSI CAD. Many studies have explored learning-based techniques for cross-stage prediction tasks in the design flow. Although building machine learning models usually requires a large amount of data, most studies can only generate small internal datasets for validation due to the lack of large public datasets. Such a situation challenges the research in this field and raises potential issues like difficulty in benchmarking and reproducing results, limited research scope on small internal datasets, and high bar for new researchers. Therefore, in this paper, we present an open-source dataset called “CircuitNet” for machine learning tasks in VLSI CAD. The dataset consists of more than 10K samples extracted from versatile runs of commercial design tools based on 6 open-source RISC-V designs which support typical cross-stage prediction tasks, such as routability and IR drop prediction, with extensive benchmarking on recent models. With the dataset prepared, we identify two practical challenges, data imbalance and model transferability, for machine learning application in CAD. To overcome data imbalance, we propose a loss function, biased loss, to give more weight to the minority, leading to 2% congestion reduction in routability driven placement. We test the model transferability from RISC-V designs to ISPD 2015 contest designs in congestion prediction with several transfer learning methods, and further proposed a knowledge distillation based transfer learning framework with up to 20% accuracy improvement. We believe this dataset can open up new opportunities for machine learning in CAD research and beyond.

Strategies for optimizing plasmonic grating couplers with a topology-based inverse design

Numerical simulations have become a cornerstone technology in the development of nanophotonic devices. Specifically, 3D finite-difference time domain (FDTD) simulations are widely used due to their flexibility and powerful design capabilities. More recently, FDTD simulations in conjunction with a design methodology called inverse design has become a popular way to optimize device topology, reducing a device’s footprint and increasing performance. We implement a commercial inverse design tool to generate complex grating couplers and explore a variety of grating coupler design methodologies. We compare the conventionally designed grating couplers to those generated by the inverse design tool. Finally, we discuss the limitations of the inverse design tool and how different design strategies for grating couplers affect inverse design performance, in terms of both computational cost and performance of the resulting device.

Implementing commercial inverse design tools for compact, phase-encoded, plasmonic digital logic devices

Numerical simulations have become an essential design tool in the field of photonics, especially for nanophotonics. In particular, 3D finite-difference-time-domain (FDTD) simulations are popular for their powerful design capabilities. Increasingly, researchers are developing or using inverse design tools to improve device footprints and performance. These tools often make use of 3D FDTD simulations and the adjoint optimization method. In this work, we implement a commercial inverse design tool with these features for several plasmonic devices that push the boundaries of the tool. We design a logic gate with complex design requirements, as well as a y-splitter and waveguide crossing. With minimal code changes, we implement a design that incorporates phase encoded inputs in a dielectric-loaded surface plasmon polariton waveguide. The complexity of the requirements in conjunction with limitations in the inverse design tool force us to make concessions regarding the density of encoding and to use on-off keying to encode the outputs. We compare the performance of the inverse-designed devices to conventionally-designed devices with the same operational behavior. Finally, we discuss the limitations of the inverse design tools for realizing complex device designs and comment on what is possible at present and where improvements can be made.

Generative Design: Reframing the Role of the Designer in Early-Stage Design Process

AbstractGenerative design tools empowered by recent advancements in artificial intelligence (AI) offer the opportunity for human designers and design tools to collaborate in new, more advanced modes throughout various stages of the product design process to facilitate the creation of higher performing and more complex products. This paper explores how the use of these generative design tools may impact the design process, designer behavior, and overall outcomes. Six in-depth interviews were conducted with practicing and student designers from different disciplines who use commercial generative design tools, detailing the design processes they followed. From a grounded theory-based analysis of the interviews, a provisional process diagram for generative design and its uses in the early-stage design process is proposed. The early stages of defining tool inputs bring about a constraint-driven process in which designers focus on the abstraction of the design problem. Designers will iterate through the inputs to improve both quantitative and qualitative metrics. The learning through iteration allows designers to gain a thorough understanding of the design problem and solution space. This can bring about creative applications of generative design tools in early-stage design to provide guidance for traditionally designed products.

VirtualSync+: Timing Optimization With Virtual Synchronization

In digital circuit designs, sequential components such as flip-flops are used to synchronize signal propagations. Logic computations are aligned at and thus isolated by flip-flop stages. Although this fully synchronous style can reduce design efforts significantly, it may affect circuit performance negatively, because sequential components can only introduce delays into signal propagations but never accelerate them. In this article, we propose a new timing model, VirtualSync+, in which signals, specially those along critical paths, are allowed to propagate through several sequential stages without flip-flops. Timing constraints are still satisfied at the boundary of the optimized circuit to maintain a consistent interface with existing designs. By removing clock-to-q delays and setup time requirements of flip-flops on critical paths, the performance of a circuit can be pushed even beyond the limit of traditional sequential designs. In addition, we further enhance the optimization with VirtualSync+ by fine-tuning with commercial design tools, e.g., design compiler from Synopsys, to achieve more accurate result. To achieve this fine-tuning, we first optimize the circuits by reallocating sequential components with sequential and combinational components as delay units. Afterward, the removal locations of flip-flops with respect to the circuits under optimization are extracted and the corresponding wave-pipelining timing constraints compatible with commercial design tools are established. These timing constraints are then incorporated into the optimization flow of commercial tools to generate the optimized circuits. The experimental results demonstrate that circuit performance can be improved by up to 4% (average 1.5%) compared with that after extreme retiming and sizing, while the increase of area is still negligible. This timing performance is enhanced beyond the limit of traditional sequential designs. It also demonstrates that compared with those after retiming and sizing, the circuits with VirtualSync+ can achieve better timing performance under the same area cost or smaller area cost under the same clock period, respectively.

HMAB

Effective physical database design tuning requires selection of several physical design structures (PDS), such as indices and materialised views, whose combination influences overall system performance in a non-linear manner. While the simplicity of combining the results of iterative searches for individual PDSs may be appealing, such a greedy approach may yield vastly suboptimal results compared to an integrated search. We propose a new self-driving approach (HMAB) based on hierarchical multi-armed bandit learners, which can work in an integrated space of multiple PDS while avoiding the full cost of combinatorial search. HMAB eschews the optimiser cost misestimates by direct performance observations through a strategic exploration, while carefully leveraging its knowledge to prune the less useful exploration paths. As an added advantage, HMAB comes with a provable guarantee on its expected performance. To the best of our knowledge, this is the first learned system to tune both indices and materialised views in an integrated manner. We find that our solution enjoys superior empirical performance relative to state-of-the-art commercial physical database design tools that search over the integrated space of materialised views and indices. Specifically, HMAB achieves up to 96% performance gain over a state-of-the-art commercial physical database design tool when running industrial benchmarks.

Robust feasibility verification and region inner-point detection algorithms for geometric shape objects applied to electric machine optimization workflow

In most cases, the search for the optimal design of an electrical machine is closely related to its 2D radial cross section. When optimizing a 2D cross section, special attention must be paid to the geometry and to the definition of the parameters along with their boundaries. Even if properly bounded, complex geometries generated by optimization algorithms can lead to geometrically infeasible candidates. These cannot be manufactured because they contain generally undesirable geometric relationships between air, magnets, and steel. Different commercial and open-source finite element analysis (FEA) design tools treat the infeasible designs differently. The results vary from simulation stop to successful FEA calculation of the infeasible candidate, which wastes time by producing useless data. To prevent the infeasible designs from entering the optimization competition and possibly appearing incorrectly as optimal solutions, and to reduce optimization time, it is important to capture the infeasible designs during optimization. Moreover, the FEA tool requires a precisely determined interior point to assign the material to each closed region (air, steel, epoxy, magnet...). This can be very challenging for complex geometries. To avoid creating geometry or material regions that are not valid, this paper proposes a novel robust methods for checking feasibility and determining interior points on geometric shape objects. In this paper, the proposed method is applied to the optimization of electrical machines.

System on Chip Noise Integrity Simulation

In mixed-signal integrated circuits, interference between digital noisy and sensitive analog/RF circuits is a challenging performance issue. The high cost of chip fabrication requires accurate simulation of the circuits’ performance versus signal and noise integrity. In this paper, a substrate crosstalk noise analysis flow is described and the characteristics of the substrate noise coupling mechanism are analyzed. The proposed noise integrity aware simulation flow properly estimates the substrate coupling effect and predicts the analog/RF victim circuit performance degradation due to noise coupling mechanisms. The methodology is implemented seamlessly in the current standard virtuoso-based design suite and is used in parallel with any commercial design tool, compatible with the standard analog/RF simulation process. The efficiency of the proposed methodology is validated by a full substrate crosstalk aware system on chip vehicle, designed in an RFCMOS 65 nm process. Silicon substrate, interconnect parasitics and package parasitics are efficiently modeled so as to enable the substrate noise simulation. A substrate crosstalk system on chip vehicle is designed in a 65 nm RFCMOS. The crosstalk noise victim is a 5 GHz CMOS LNA and the noise aggressor is a 90 kGates digital logic. It is demonstrated that by applying the proposed methodology, substrate crosstalk performance degradation can be efficiently captured. The LNA carrier degradation and the spectrum distortion re efficiently simulated by identifying all of the noise spurs propagating through the common silicon substrate from the digital logic to the custom low noise amplifier noise victim. The respective inter-modulation spurs are also captured.

Physical based compact model of Y-Flash memristor for neuromorphic computation

Y-Flash memristors utilize the mature technology of single polysilicon floating gate nonvolatile memories. It can be operated in a two-terminal configuration similar to the other emerging memristive devices, e.g., resistive random-access memory and phase-change memory. Fabricated in production complementary metal-oxide-semiconductor technology, Y-Flash memristors allow excellent reproducibility reflected in high neuromorphic products yields. Working in the subthreshold region, the device can be programmed to a large number of fine-tuned intermediate states in an analog fashion and allows low readout currents (1 nA ∼ 5 μA). However, currently, there are no accurate models to describe the dynamic switching in this type of memristive device and account for multiple operational configurations. In this paper, we provide a physical-based compact model that describes Y-Flash memristor performance in both DC and AC regimes and consistently describes the dynamic program and erase operations. The model is integrated into the commercial circuit design tools and is ready to be used in applications related to neuromorphic computation.

Hybrid modeling approach for mode-locked laser diodes with cavity dispersion and nonlinearity

Semiconductor-based mode-locked lasers, integrated sources enabling the generation of coherent ultra-short optical pulses, are important for a wide range of applications, including datacom, optical ranging and spectroscopy. As their performance remains largely unpredictable due to the lack of commercial design tools and the poorly understood mode-locking dynamics, significant research has focused on their modeling. In recent years, traveling-wave models have been favored because they can efficiently incorporate the rich semiconductor physics of the laser. However, thus far such models struggle to include nonlinear and dispersive effects of an extended passive laser cavity, which can play an important role for the temporal and spectral pulse evolution and stability. To overcome these challenges, we developed a hybrid modeling strategy by unifying the traveling-wave modeling technique for the semiconductor laser sections with a split-step Fourier method for the extended passive laser cavity. This paper presents the hybrid modeling concept and exemplifies for the first time the significance of the third order nonlinearity and dispersion of the extended cavity for a 2.6 GHz III–V-on-Silicon mode-locked laser. This modeling approach allows to include a wide range of physical phenomena with low computational complexity, enabling the exploration of novel operating regimes such as chip-scale soliton mode-locking.

Design and tool flow of a reconfigurable asynchronous neural network accelerator

Convolutional Neural Networks (CNNs) are widely used in computer vision, natural language processing, and so on, which generally require low power and high efficiency in real applications. Thus, energy efficiency has become a critical indicator of CNN accelerators. Considering that asynchronous circuits have the advantages of low power consumption, high speed, and no clock distribution problems, we design and implement an energy-efficient asynchronous CNN accelerator with a 65 nm Complementary Metal Oxide Semiconductor (CMOS) process. Given the absence of a commercial design tool flow for asynchronous circuits, we develop a novel design flow to implement Click-based asynchronous bundled data circuits efficiently to mask layout with conventional Electronic Design Automation (EDA) tools. We also introduce an adaptive delay matching method and perform accurate static timing analysis for the circuits to ensure correct timing. The accelerator for handwriting recognition network (LeNet-5 model) is implemented. Silicon test results show that the asynchronous accelerator has 30% less power in computing array than the synchronous one and that the energy efficiency of the asynchronous accelerator achieves 1.538 TOPS/W, which is 12% higher than that of the synchronous chip.

Generating minimal Pareto sets in multi-objective topology optimisation: an application to the wing box structural layout

Multi-objective topology optimisation problems are often tackled by compromising the cost functions according to the designer’s knowledge. Such an approach however has clear limitations and usually requires information which especially at the preliminary design stage could be unavailable. This paper proposes an alternative multi-objective approach for the generation of minimal Pareto sets in combination with density-based topology optimisation. Optimised solutions are generated integrating a recently revised method for a posteriori articulation of preferences with the Method of Moving Asymptotes. The methodology is first tested on an academic two-dimensional structure and eventually employed to optimise a full-scale aerospace structure with the support of the commercial software Altair OptiStructⓇ. For the academic benchmark, the optimised layouts with respect to static and dynamic objectives are visualised on the Pareto frontier and reported with the corresponding density distribution. Results show a progressive and consistent transition between the two extreme single-objective layouts and confirm that the minimum number of evaluations was required to fill the smart Pareto front. The multi-objective strategy is then coupled with Altair OptiStruct and used to optimise a full-scale wing box, with the clear purpose to fill a gap in multi-objective topology optimisation applied to the wing primary structure. The proposed methodology proved that it can generate efficiently non-dominated optimised configurations, at a computational cost that is mainly driven by the model complexity. This strategy is particularly indicated for the preliminary design phase, as it releases the designer from the burden to assign preferences. Furthermore, the ease of integration into a commercial design tool makes it available for industrial applications.

FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications

Application-specific instruction-set processors (ASIPs) utilize customized instructions to speedup a specific application or a set of applications. Thus, ASIPs execute the application(s) faster and are energy efficient compared to general-purpose processors. State-of-the-art custom instruction design methods typically target small applications or kernels of an application, often demanding an instruction designer's ingenuity at some point (semi-automated) to achieve design goals. In this article, for the first time, a fully automated system called FINDER is presented, which finds parallel instructions for ASIPs to improve the performance of large applications and generate FLIX (flexible instructions extension instructions, which are VLIW-type instructions) configurations. Note that we do not synthesize accelerators to speedup. We demonstrate that the proposed method scales well when applied to large applications. The proposed method described in this article models parallel instructions as a graph, analyzes the graph, and finds maximum weighted cliques to create FLIX configurations for a given application. Moreover, hardware reuse within multiple FLIX configurations is incorporated into the methodology. From the configurations, a commercial processor design tool (Xtensa) creates the FLIX instructions and integrates it into a base processor. The results show that the FINDER methodology generates FLIX configurations which shows speedups of up to 2.1× for large applications and 2.7× for smaller applications when compared to the base processor (without FLIX instructions). The logic area increase on average is 11%, and in the worst case is 22%. The energy-delay product can be up to 7.3× lower than when the application is executed on the base processor. Compared to the state-of-the-art systems which are typically demonstrated on applications with less than 100 lines of code, FINDER is capable of analyzing applications with thousands of lines of code and can automatically generate instructions for such applications.

Linear Power Flow Method Improved With Numerical Analysis Techniques Applied to a Very Large Network

In this paper, we propose a fast linear power flow method using a constant impedance load model to simulate both the entire Low Voltage (LV) and Medium Voltage (MV) networks in a single simulation. Accuracy and efficiency of this linear approach are validated by comparing it with the Newton power flow algorithm and a commercial network design tool Vision on various distribution networks including real network data. Results show that our method can be as accurate as classical Nonlinear Power Flow (NPF) methods using a constant power load model and additionally, it is much faster than NPF computations. In our research, it is shown that voltage problems can be identified more efficiently when MV and LV are integrally evaluated. Moreover, Numerical Analysis (NA) techniques are applied to the Large Linear Power Flow (LLPF) problem with 27 million nonzeros in order to improve the computation time by studying the properties of the linear system. Finally, the original computation times of LLPF problems with real and complex components are reduced by 2.8 times and 5.7 times, respectively.

Data Changes Everything: Challenges and Opportunities in Data Visualization Design Handoff.

Complex data visualization design projects often entail collaboration between people with different visualization-related skills. For example, many teams include both designers who create new visualization designs and developers who implement the resulting visualization software. We identify gaps between data characterization tools, visualization design tools, and development platforms that pose challenges for designer-developer teams working to create new data visualizations. While it is common for commercial interaction design tools to support collaboration between designers and developers, creating data visualizations poses several unique challenges that are not supported by current tools. In particular, visualization designers must characterize and build an understanding of the underlying data, then specify layouts, data encodings, and other data-driven parameters that will be robust across many different data values. In larger teams, designers must also clearly communicate these mappings and their dependencies to developers, clients, and other collaborators. We report observations and reflections from five large multidisciplinary visualization design projects and highlight six data-specific visualization challenges for design specification and handoff. These challenges include adapting to changing data, anticipating edge cases in data, understanding technical challenges, articulating data-dependent interactions, communicating data mappings, and preserving the integrity of data mappings across iterations. Based on these observations, we identify opportunities for future tools for prototyping, testing, and communicating data-driven designs, which might contribute to more successful and collaborative data visualization design.

Targeted modification of hardware trojans

The use of untrusted design tools, components, and designers, coupled with untrusted device fabrication, introduces the possibility of malicious modifications being made to integrated circuits (ICs) during their design and fabrication. These modifications are known as hardware trojans. The widespread use of commercially purchased 3rd party intellectual property (3PIP) and commercial design tools extends even into trusted design flows. Unfortunately, due to the theoretical result that there is no program that can decide whether any other program will eventually halt, we know that the properties of a program, or circuit, cannot be known in advance of running it. While we can design a circuit to meet some functional specification and generate a simulation or test suite to obtain at least probabilistic confidence that the circuit implements the intended functionality, we cannot test a circuit for unintended functionality due to the combinatorially large state space. To address these concerns, we have developed a design-time method for automatically and systematically modifying portions of a design that exhibit characteristics of hardware trojans. After each modification, the functionality of the design is verified against a comprehensive simulation suite to ensure that the intended circuit functionality has not been changed. This approach can be applied to any digital circuit and does not rely on secret keys or obfuscation.

A New Physical Insight for the 3-D-Layout-Induced Cylindrical Breakdown in Lateral Power Devices on SOI Substrate

The layout-induced cylindrical breakdown may occur as a result of the multifinger or circular layout-induced 3-D curvature effect resulting in the breakdown voltage reduction of the power device significantly. In this paper, by using effective doping concentration (EDC) concept, the inherent 3-D problem is simplified as a 1-D problem. Based on the EDC concept, a 1-D analytical model is presented to qualitatively and quantitatively explore the impact of curvature effect on the breakdown mechanism of SOI lateral double diffused MOS. The analytical solutions are found out to be consistent with the simulation results well obtained from MEDICI, a commercial technology computer-aided design tool. To the best of our knowledge, the proposed model is the first 1-D model which can accurately describe the 3-D curvature effect.

A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits

In this paper, a variation-aware simulation framework for hybrid circuits comprising MOS transistors and magnetic tunnel junction (MTJ) devices is presented. The framework is based on one-time characterization via micromagnetic multi-domain simulations, overcoming the inaccuracies introduced by single-domain analysis, which most of the existing frameworks are based on. As further distinctive capability, non-Gaussian stochastic variations of the MTJ write switching time are explicitly modeled through a Skew Normal distribution, making the model suitable for low-power and low-voltage designs. The framework involves the use of a Verilog-A look-up table-based model, which assures easy integration with commercial design tools. Our strategy is evaluated on a spin-transfer torque-magnetoresistive random access memory (MRAM) working in RAM and true random number generator (TRNG) modes. In RAM mode, while the commonly-used approach based on Gaussian-distributed switching statistics tends to underestimate the pulse width required for a write error rate of $10^{-6}$ by about 20%, our Skew Normal-based strategy allows tracking reference micromagnetic results with an average error less than 4%. In TRNG mode, our approach also allows a better tracking of the reference 50%-switching probability contour with an error less than 1%abs. However, the incorporation of the Skew Normal distribution in our Verilog-A model results in an increase of the CPU time by 50% on average as compared with the use of the built-in statistical functions.

Analysis of Low-Grade Waste Heat Driven Systems for Cooling and Power for Tropical Climate

In the 21st conference of the parties (COP21) of United Nations, both renewable energy and energy efficiency were recognized as essential means for low-carbon future. It is estimated that around 20-50 % of energy input to industries is lost as waste heat. Low-grade heat is abundantly available from renewable sources like solar, biomass and geothermal. There is a need to develop technologies which can utilize very low-grade heat (<100 °C). This paper reports the design and optimization of heat driven systems for utilizing very low-grade waste heat in tropical conditions. The Ejector Refrigeration System (ERS) has been selected, designed and simulated to producing cooling from low-grade heat. Organic Rankine Cycle (ORC) has been designed and simulated for producing power and a novel hybrid configuration is proposed to produce power and cooling simultaneously. The ERS and ORC optimization involves the selection of most suitable working fluids, working conditions, sizing of components, and optimizing configurations. For system level modeling with real properties of working fluids, EES (engineering equation solver) and EBSILON (a commercial thermal system design tool) are being used in this work. For design optimization of ejector, EES and ANSYS-FLUENT (a commercial CFD solver) are being used. With EES model, the ORC system has been found to operate at 5.2 % overall efficiency. The results from EES model have been verified by the EBSILON model. The EES model for ERS gives the COP of 0.48. The EES model developed for ejector nozzles can be used to design any supersonic nozzle for the desired inlet and outlet pressers and exit velocity. A novel hybrid cycle configuration has been proposed. This novel configuration uses ejector simultaneously for two purposes; to reduce the work-producing-expander outlet pressure and to compress vapor for cooling cycle. The preliminary modeling results show that the output of this configuration is 27 % higher than simple ORC.