Commercial Computer-aided Design Tools Research Articles

Superconducting Digital Circuit Design With an Open Source and Freeware Tool Chain

Superconducting digital circuits have been around for decades, but recent projects that exploit such circuits for low-power, high-performance computing are rapidly maturing superconducting circuit technologies. As a result of increasing circuit complexity, there is renewed focus on superconducting digital circuit design tools. Until now, most computer-aided design (CAD) tool development for superconducting electronics (SCE) circuit design has been based on calibrating semiconductor tools, rather than creating new technology-specific tools for the SCE circuit design. The recent development shows bias toward large and expensive CAD tools. These tools, or modules developed for commercial semiconductor CAD tools, require users to have access to an expensive commercial semiconductor CAD software, which places it out of the reach of new entrants or small research groups in SCE. In this paper, the open-source tools that can be used as alternatives to form an SCE design tool chain are described. All the design stages in an SCE integrated circuits design flow, from circuit specification down to layout design, are noted in this paper. Each stage is discussed and the available open-source tools are described. The inherent disadvantages of these open-source tools are also pointed out. A design example is then provided to demonstrate a complete open source and freeware tool chain.

A Fully Nonlinear Compact Modeling Approach for High-Frequency Noise in Large-Signal Operated Microwave Electron Devices

A technology-independent, inherently nonlinear approach is proposed for the compact modelling of high-frequency noise in microwave transistors under large-signal operating conditions. For the compact nonlinear noise model formulation we assume that noise generation can be described by a suitable set of distributed stochastic processes perturbing a very general, non-quasi-static deterministic description of the electron device, in accordance with the strategies adopted in physics-based methods for the choice and exploitation of microscopic diffusion noise sources. The propagation of the internal distributed noise sources up to the intrinsic device terminals leads to a set of non-stationary, correlated equivalent noise generators, nonlinearly controlled by the instantaneous large-signal working point of the device. Starting from a first formulation for the generators, formally derived from a physics-based description of the noise generation mechanisms widely adopted in distributed numerical modeling, mild approximations provide a fully behavioral representation that can be empirically extracted on the basis of measurement data only, and can be easily implemented into commercial computer-aided design tools by means of conventional, uncorrelated noise sources. As far as small-signal (i.e., linear) bias-dependent operation is concerned, it is shown how well-known, widely applied compact models for high-frequency noise can be considered as linearized special cases of the proposed approach. For a full validation, experimental examples are provided, both in small- and large-signal operation, for a GaAs-pHEMT, by considering the case study of a broad-band low-noise amplifier progressively driven into nonlinear regime by an increasing power interferer.

A Volterra-Based Procedure for Multi-Port and Multi-Zone GaN FET Amplifier CAD Simulation

This paper reports a systematic method for the computer-aided-design (CAD) simulation of GaN FET power amplifiers (PAs). The core of the proposal is a Volterra-based behavioral model (BM) with multi-spectral and multi-node capabilities, which black-box structure is formally derived from a circuit-level representation of the PA and accounts for both short and long-term memory effects. Starting with the equivalent circuit of a typical FET device with thermal power feedback, the structures of the kernels for the gate, drain and thermal nodes are developed and are shown to be dependent on the frequency response of the PA terminating impedances and thermal filter. The model has been applied to simulate the nonlinear response of a typical PA circuit, showing the ability of the proposed model to provide an accurate prediction of multi-spectral, multi-node characteristics, including AM/AM-AM/PM conversion, spectral regrowth, intermodulation, and temperature rise, under diverse input signal waveforms and bandwidths. These results have been successfully compared with commercial CAD tools based on harmonic balance or envelope simulation.

Spatial distribution of fluence rate from upper-room ultraviolet germicidal irradiation: Experimental validation of a computer-aided design tool

A commercial computer-aided design tool used by the lighting industry was modified to predict fluence rates for upper-room ultraviolet germicidal irradiation. Experimental validation based on more than 1600 measurements and 3 types of commercial ultraviolet fixtures, which was done in an experimental chamber and in a homeless shelter having fixtures in continuous use for over 7 years, showed differences in measured and predicted average upper-room fluence rates of less than 10%. The computer-aided design tool, however, was not very successful at predicting fluence rates at specific room locations, a capability that is needed for mating computational fluid dynamics with ultraviolet germicidal irradiation. Although not an objective of this study, it was also found that the three types of fixtures used in this study have surprisingly significant differences in efficiency based on fixture ultraviolet power output and electrical input. One fixture type had an efficiency that was more than five times that of another. For comparison purposes, a standard method for measuring and reporting fixture efficiency is needed.

INTEGRATION OF CAD AND CAE IN SME’S FOR PRODUCT DEVELOPMENT

Small manufacturing enterprises face a number of challenges when integrating computer aided design (CAD) tools and computer-aided engineering (CAE) tools into their design processes. One of the most significant challenges is interoperability across the wide range of commercial CAD and CAE tools. Although many of these tools support industry data standards and claim to be interoperable, the connection between them is not seamless. This paper summarizes studies of tool integration activities at one small manufacturer. The paper shows the enhancement of the product development process resulting from replacement of a two dimensional CAD system with a three-dimensional CAD system and creation of an inhouse capability to perform finite element analysis (FEA), replacing analysis that had previously been outsourced. As a result of these experiences, the manufacturer learned that improved productivity and superior designs could be obtained by integrating analysis into the design process at the earlier stages of conceptual and preliminary design.

SpiNNaker

The design and implementation of globally asynchronous locally synchronous systems-on-chip is a challenging activity. The large size and complexity of the systems require the use of computer-aided design (CAD) tools but, unfortunately, most tools do not work adequately with asynchronous circuits. This article describes the successful design and implementation of SpiNNaker, a GALS multicore system-on-chip. The process was completed using commercial CAD tools from synthesis to layout. A hierarchical methodology was devised to deal with the asynchronous sections of the system, encapsulating and validating timing assumptions at each level. The crossbar topology combined with a pipelined asynchronous fabric implementation allows the on-chip network to meet the stringent requirements of the system. The implementation methodology constrains the design in a way that allows the tools to complete their tasks successfully. A first test chip, with reduced resources and complexity was taped-out using the proposed methodology. Test chips were received in December 2009 and were fully functional. The methodology had to be modified to cope with the increased complexity of the SpiNNaker SoC. SpiNNaker chips were delivered in May 2011 and were also fully operational, and the interconnect requirements were met.

Engineering design and realisation of an automatic real time weather monitoring station using commercial CAD tools

The paper describes the design and realisation of a low cost automatic real time weather station project aimed at significantly enhancing the design, realisation, and testing skills of undergraduate engineering students through the use of industrial Computer Aided Design (CAD) tools. The station measures the following meteorological variables: temperature, humidity, rain, and wind speed and direction. It has a wireless RF module to relay data to a computer, which displays, saves, and archives weather data. During the course of this project, software tools are used to speed up the design process. As a result, such tools allow students to not only design but also to redesign. It is only by redesign and experimentation that students learn how design problems interact and how to trade off competing issues.

Architectural-Level Power Optimization of Microcontroller Cores in Embedded Systems

Power saving is becoming one of the major design drivers in electronic systems embedding microcontroller cores. Known microcontrollers typically save power at the expense of reduced computational capability. With reference to an 8051 core, this paper presents a novel clustered clock gating to increase power efficiency at architectural level without performance loss and preserving the reusability of the macrocell. Different from known clustered-gating strategies where the number of clusters is fixed a priori, the optimal cluster organization is derived, considering both the macrocell complexity and switching activity. When implementing the 8051 core in CMOS technology, the proposed approach leads to a 37% power saving, which is higher than the 29% permitted by automatic-clock-gating insertion in commercial computer-aided design tools or the 10% of state-of-the-art clustered-gating strategies. To assess its full functionality, the power-optimized cell has been proved in silicon that is embedded in an automotive system for sensors interface/control

Stability Criterion for Two-Port Network With Input and Output Terminations Varying in Elliptic Regions

New criteria to check the conditional stability of microwave amplifiers with input and output terminations varying in prespecified elliptic regions surrounding complex nominal values are proposed. Necessary and sufficient conditions are provided in terms of the immittance parameters lambdaij (i.e., zij, yij, gij, or hij): these conditions can be implemented in commercial computer-aided design tools and are suitable to be used as design goals within optimization routines. Since elliptic shapes accurately fit the real variability region of input and output terminations, the proposed criterion allows to impose stability in the actual tolerance range of terminations and therefore to improve the tradeoff between performance and stability under termination variations

Scalable Model of On-Wafer Interconnects for High-Speed CMOS ICs

This paper describes the development of an equivalent circuit model of on-wafer interconnects for high-speed CMOS integrated circuits. By strategically cascading two-pi blocks together, the lumped model can characterize the distributed effects. Besides, the elaborately proposed model characterizes the frequency-variant characteristics with frequency-independent components. Thus, the model can be easily plugged into commercial computer-aided design tools. By adopting a newly invented optimization algorithm, namely, particle swarm optimization (PSO), the model parameters are extracted and formulated as empirical expressions. Therein, with each set of the geometrical parameters, the interconnect behaviors can be accurately predicted. The accuracy of the model is validated by comparisons with the on-wafer measurements up to 30 GHz. Moreover, the scalability of the proposed model is also discussed

Necessary and sufficient conditions for the stability of microwave amplifiers with variable termination impedances

New criteria to check conditional stability of microwave amplifiers with input and output terminations varying in pre-specified circular regions surrounding complex nominal values are proposed. Necessary and sufficient conditions are provided both in terms of the immittance parameters /spl lambda//sub ij/ (i.e., z/sub ij/,y/sub ij/,g/sub ij/, or h/sub ij/) and in terms of the scattering parameters s/sub ij/. Proposed conditions can be easily implemented in any commercial computer-aided design tool and are suitable to be used as design goals within an optimization routine: this allows to optimize the tradeoff between stability constraints under termination variations and performance in a yield-oriented design flow. A case study, in which a distributed amplifier has been designed, shows the advantages of the proposed approach.

An introductory digital design course using a low-cost autonomous robot

This paper describes a new digital design laboratory developed for undergraduate students in this electrical and computer engineering curriculum. A top-down rapid prototyping approach with commercial computer-aided design tools and field-programmable logic devices (FPLDs) is used for laboratory projects. Students begin with traditional transistor-transistor logic-based projects containing a few gates and progress to designing a simple 16-bit computer, using very high-speed integrated circuits hardware description language (VHDL) synthesis tools and an FPLD. To help motivate students, the simple computer design is programmed to control a small autonomous robot with two servo drive motors and several sensors. The laboratory concludes with a team-based design project using the robot.

False path exclusion in delay analysis of RTL structures

In this paper, we present an accurate delay-estimation algorithm at the register-transfer level. We study three important sources of false paths in register-transfer-level (RTL) structures, i.e., 1) resource binding; 2) interdependent conditions; and 3) datapath-controller path mismatching. The existence and creation of such paths and their effects in delay analysis are discussed. We show that in a RTL datapath structure the accuracy of the delay estimators is affected by the existence of false paths. Specifically, the accuracy drops significantly for structures synthesized from condition-dominated behaviors. We propose a mechanism to efficiently avoid false paths in delay analysis. This is achieved by introducing the propagation delay graph (PDG), whose traversal for delay analysis is equivalent to the traversal of sensitizable paths in the datapath. Comparison with the timing verifier in commercial computer-aided design (CAD) tools, show that estimated delays are within 14% accuracy of those reported by CAD tools.

Low loss multilayer microstrip line for monolithic microwave integrated circuits applications

This paper describes the multilayer microstrip structure using low dielectric constant polyimide as a buffer layer between the microstrip conductor and the GaAs substrate to reduce dissipation loss, especially for very high impedance microstrip lines. The new structure provides about half the dissipation loss and about 40% higher characteristic impedance in comparison to the conventional microstrip line on GaAs substrate having the same conductor widths. An empirical formula for the equivalent dielectric constant compatible with commercial computer-aided design tools was developed to design monolithic microwave integrated circuits (MMICs) using this medium. The multilayer microstrip structure is compatible with ITT's 4′ MSAG® process which uses polyimide for crossovers and scratch protection. The present structure has great potential in realizing low loss and wideband matching networks including low noise, high power, and high efficiency amplifiers, and passive components on GaAs substrate with improved insertion loss and bandwidth performance, and three-dimensional MMICs. © 1998 John Wiley & Sons, Inc. Int J RF and Microwave CAE 8: 441–454, 1998