Combinational Switching Circuits Research Articles

A theory for the derivation of combinational C-mos circuit designs

This paper shows how propositional logic may be used to reason about synchronous combinational switching circuits implemented in C-mos. It develops a simple formalism and theory for describing and predicting their behaviour. On this it builds a calculus of design which is driven by proof obligations. The design philosophy for software introduced in [1] is thereby extended to a certain kind of hardware design. No prior knowledge of hardware is assumed of the reader; but useful background, motivation, examples and pictures may be found in [2]. Many of the problems described in that paper have been solved in this one.

Ternary Representation of Zero Cubes in the Design of Combinational Switching Circuits

The logical behaviour of a combinational switching circuit can be represented by a boolean function. The boolean function can be simpliied to another equivalent function which minimises the number of gates in the circuit.The karnaugh map is a very powerful tool in minimising switching functions of upto six variables. In order to manipulate functions of a larger number of variables, a systematic procedure which can be programmed for a digital computer can be developed by Quine Mc-cluskey method.To implement the Quine Mc-cluskey method, the basis is min terms of switching function which can be written in cube form called zero cubes. The zero cubes are to be grouped in order of increasing number of 1s in each zero cube. One cubes can be generated from zero cubes using bit strings to represent cubes. Only values 0 and 1 appear in a bit string. Hence, a different convention called Ternary representation of cubes is essential.A systematic procedure for grouping zero cubes in order of increasing number of 1s and for getting Ternary representation of zero cubes has been developed and programmed in ASSEMBLY LANGUAGE and implemented on Microprocessor.

An Examination of the Cost Function for Programmable Logic Arrays

Cost functions for combinational switching circuits are commonly defined as monotonically increasing functions of the number of gates and the number of inputs. The structure of programmable logic arrays (PLA's) is such that the cost is more aptly only dependent on gate quantity. The consequences of redefining cost for PLA's are studied with respect to covering algorithms. The major benefits are that a multiple output prime implicant (implicate) table can be viewed as a single output table and that minimal covers can be determined much more simply, especially for cyclic tables.

Detection of Hazards in Combinational Switching Circuits

This correspondence investigates a systematic binary technique for detecting static and dynamic hazards in combinational networks. The technique is based on deriving the conditions for the occurrence of spikes and considering a hazard as a superposition of spikes.

An Approach to Unified Methodology of Combinational Switching Circuits

A methodology based on the theory of Boolean equations has been developed which permits a unified approach to the analysis and synthesis of combinational logic circuits. The type of circuits covered by the approach includes both the classical loopless combinational networks as well as those that contain closed feedback loops and thus have internally a sequential character. To that end, a general multiple-output circuit represented by a Mealy-type machine is studied using characteristic equations (functions) that describe its internal structure. It is shown how behavioral properties of the circuit are reflected through the sosutions of these equations. Moreover, it is demonstrated that a multiple-output incompletely specified switching function is reaeized if a ≤ relation is satisfied between the corresponding charchteristic functions. This leads to a new unified outlook on functional decomposition as used in modular synthesis procedures. Although the building modules are allowed to be sequential circuits, it is shown under which conditions the feedback loops are redundant with respect to the realization of a given output characteristic function, and thus the existence conditions of nondegenerate combinational circuits with loops are stated.

Applications of fuzzy algebra to hazard detection in combinational switching circuits

This paper presents some theoretical considerations for the detection of hazards in combinational switching systems. The application of fuzzy models to hazard detection in binary systems is discussed, and this leads to methods of detection for multiple zero and one hazards. Finally, a method for theorem proving applicable to the detection method is presented.

The elimination of erroneous effects of fuction hazards in combinational switChing circuits

The elimination of erroneous effects of fuction hazards in combinational switChing circuits

Comments on "Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences"

This correspondence comments on certain aspects of a recent paper1 by Marinos relating to derivation of minimal complete sets of test-input sequences to detect stuck-at faults in combinational switching circuits utilizing the concept of Boolean difference. The primary motivation behind this move is to mention some minor inconsistencies, inaccuracies, and deficiencies involving certain key concepts of the paper, and also to generalize some useful results of the author, adding thereby to the utility and worth of the contribution.

Decomposition methods for computer-aided synthesis of combinational switching circuits : Kjelkerud, E. Royal Inst. of Tech., Sweden (1972) 8 pp, 12 ref.

Decomposition methods for computer-aided synthesis of combinational switching circuits : Kjelkerud, E. Royal Inst. of Tech., Sweden (1972) 8 pp, 12 ref.

A Design Procedure for Fault-Locatable Switching Circuits

A technique to design fault-locatable combinational switching circuits is given. The networks resulting from the application of the proposed technique have at most three levels of gates.

A Computer Program for the Synthesis of Switching Circuits by Decomposition

A computer program, which has a Boolean expression and a functionally complete set of switching functions as input data and as output data, gives a description of a logic diagram that shows the synthesized switching circuit realizing the Boolean expression, is described in this paper. The program utilizes a new proof for a generalized version of a theorem that was first stated by Ashenhurst. It is shown that an implementation of a modified form of the decomposition chart technique is indeed useful for the synthesis of combinational switching circuits.

The Description and Use of Register-Transfer Modules (RTM's)®

This note describes a set of register-transfer modules (RTM's) that are used as a basis for digital systems design. RTM's allow digital systems to be specified in a flow chart form with complete construction (wiring) information, thus obviating combinational and sequential switching circuit theory based design. The modules make extensive use of integrated circuitry. The note briefly describes the class of problems that RTM's can be used to solve, together with some of the module design decisions. The most important RTM's are described from the user's viewpoint, and two example designs are given.

Elimination of static and dynamic hazards for multiple input changes in combinational switching circuits

This paper deals with hazards on outputs of combinational switching circuits for multiple input changes. Certain types of function hazards are defined and are shown to be impossible to eliminate with any logic realization. Also, an interrelation between static and dynamic function hazards is established. Hazards due to delays in the logic are defined and a method of elimination is given for both the static and dynamic case.

Designing Sets of Fault-Detection Tests ror Combinational Logic Circuits

This paper is concerned with the problem of determining, by means of terminal experiments, whether a given combinational switching circuit operates correctly or is impaired by some malfunction. We shall be primarily concerned with permanent faults due to component failures. It is assumed that other methods will be employed to protect the circuit against the effects of transient faults. A procedure is presented for the detection of failures in combinational switching circuits. The procedure provides minimal sets of tests for two-level circuits and nearly minimal sets of tests for most multilevel circuits.

Recognition of Monotonic and Unate Cascade Realizable Functions Using an Informational Model of Switching Circuits

A model of combinational switching circuits used as information processors is described. A set of entropies (in the information theory sense) can be associated with each completely specified function, and can be easily computed from the truth table representation for the function. It is shown that simple arithmetic relations between the magnitudes of these entropies are sufficient to identify monotonic and unate functions and functions realizable as a unate cascade. In the latter case, a simple test identifies unate cascade realizable functions and gives the set of possible orderings of variables in the realization.

Detection of failures in combinational digital circuits

The paper is concerned with the problem of determining, by terminal experiments, whether a given combinational switching circuit operates correctly or whether it is impaired by some malfunction. We shall be primarily concerned with permanent faults due to component failures. It is assumed that other procedures will be employed to protect the circuit against the effects of transient faults. A method is presented for the detection of failures in combinational switching circuits. The method provides minimal sets of tests for 2-level circuits and nearly minimal sets of tests for multilevel circuits.

Switching rates of combinational switching circuits

Switching rates of combinational switching circuits

Some Aids to the Detection of Hazards in Combinational Switching Circuits

The detection of hazards in combinational switching networks can be accomplished by Boolean algebra if the independence of component states during transients is taken into account. In this note, several new techniques for carrying out such analysis are introduced. It is also shown that certain ambiguities in previous analysis procedures can lead to incorrect conclusions regarding the presence of dynamic hazards.

Maxterm Type Expressions of Switching Functions and Their Prime Implicants

One of the basic problems of combinational switching circuit theory is that of designing circuits with a minimum number of AND-gates or prime implicants. Algorithms have been formulated for this purpose which first generate all possible prime implicants corresponding to a specified switching function and then select minimal subsets of these prime implicants for use in the formation of the minimal networks [1]-[6]. In practically all the currently available methods of simplification of switching functions, use is made of the minterm type expression specified in the algebraic or its equivalent binary or decimal form. Operations with binary or decimal numbers have become very popular because of their inherent advantages.

Hazard Detection in Combinational and Sequential Switching Circuits

This paper is concerned with a unified approach to the detection of hazards in both combinational and sequential circuits through the use of ternary algebra. First, hazards in a combinational network resulting from the simultaneous changing of two or more inputs are discussed. A technique is described that will detect hazards resulting from both single- and multiple-input changes. The various types of hazards connected with gate-type sequential circuits are also discussed, and a general technique is described that will detect any type of hazard or race condition that could result in an incorrect terminal state. This technique could be easily implemented in a computer program which would be capable of detecting hazards in circuits containing hundreds of logic blocks.