Combination Of Dry Etching Research Articles

Vertical few-layer graphene/metalized Si-nanocone arrays as 3D electrodes for solid-state supercapacitors with large areal capacitance and superior rate capability

A strategy to promote the energy density of graphene-based supercapacitors by a combination of dry etching and chemical vapor deposition (CVD) techniques is demonstrated. A three dimensional (3D) electrode is composed of vertically oriented graphene that is deposited on metalized silicon nanocones. The design of the 3D electrodes improves specific surface area, electrolyte ion migration and electrical contact, resulting in an enhancement of areal capacitance and rate capability. Furthermore, a solid-state supercapacitor was prepared based on the 3D graphene electrodes and gel polymer electrolyte. The 3D electrode with 10min of CVD growth of graphene endows the electrical double layer capacitor with the highest areal capacitance of 667.2μFcm−2, which is larger than that of supercapacitors with flat electrodes.

Novel fabrication process for sub-micron interdigitated electrode arrays for highly sensitive electrochemical detection

Interdigitated electrode arrays (IDAs) are often used for electrochemical detection using redox cycling for signal amplification. Its geometry, especially the gap width, is an important factor defining its electrochemical performance (sensitivity and collection efficiency). Minimal defect density on a wafer is a must, as a single shortcut prevents the function of the sensor chip. Therefore, the fabrication of interdigitated electrode arrays is a fundamental step in the integration of electrochemical sensors. This paper presents a novel fabrication approach that allows electrode spacing in the sub-micrometer region by using standard equipment such as UV Mask Aligner, physical vapor deposition and diffusion furnace. The fabrication procedure is a combination of dry etching, thermal oxidation and wet etching. This approach has potential to realize electrode distances down to 140nm or even less. The proposed method enables the fabrication of sub-micron IDAs with the use of a conventional Mask Aligner and standard silicon technology. Moreover, it allows the electrode spacing adjustment without changing the mask design. The presented results demonstrate high sensitivity electrochemical sensors with amplification factors more than 12 without the need of e-beam lithography. Hence, this fabrication method offers a low-cost alternative to sub-micron e-beam written IDAs.

Fabrication of large-area nano-scale patterned sapphire substrate with laser interference lithography

Periodic triangle truncated pyramid arrays are successfully fabricated on the sapphire substrate by a low-cost and high-efficiency laser interference lithography (LIL) system. Through the combination of dry etching and wet etching techniques, the nano-scale patterned sapphire substrate (NPSS) with uniform size is prepared. The period of the patterns is 460 nm as designed to match the wavelength of blue light emitting diode (LED). By improving the stability of the LIL system and optimizing the process parameters, well-defined triangle truncated pyramid arrays can be achieved on the sapphire substrate with diameter of 50.8 mm. The deviation of the bottom width of the triangle truncated pyramid arrays is 6.8%, which is close to the industrial production level of 3%.

Monolithically Lens-Integrated Photonic Device Arrays for Compact Optical Transceivers

Monolithically lens-integrated surface-emitting distributed-feedback (DFB) laser arrays and p–i–n photodiode arrays were developed. A combination of dry etching and wet chemical etching was used to fabricate a monolithic InP lens. The lens profile within ±10 µm from the lens center was estimated to be parabolic shape, which is ideal for the collimation of a Gaussian beam. A fabricated lens-integrated surface-emitting DFB laser exhibited a circular, narrow far-field pattern with full-width at half maximums of 3.9×3.5°. An efficient direct coupling of the lens-integrated DFB laser to a single-mode fiber with a coupling efficiency of -3 dB was confirmed. A four-channel lens-integrated surface-emitting laser array and a lens-integrated p–i–n photodiode array were used to fabricate a very compact 100 Gbps (25 Gbps × 4 channel) optical transceiver with 14×9 mm2 footprint.

Fabrication and transport properties of 12CaO·7Al2O3 (C12A7) electride nanowire

AbstractElectron‐doped 12CaO·7Al2O3 (C12A7) nanowires (NWs) were fabricated by two approaches. First, spatially selective electron doping of C12A7 films was examined by using a chemical method specific to C12A7. However, the conductive NW was not formed due to diffusion of oxygen in the C12A7 films to the conductive area. Secondly, a combination of dry etching and electron doping was examined. NWs with conductivities ∼6 S/cm at 300 K were successfully fabricated by this method. The temperature dependence of the conductivity in the NWs exhibited almost degenerated conduction down to 5 K. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Fabrication of Silicon and Germanium Nanostructures by Combination of Hydrogen Plasma Dry Etching and VLS Mechanism

Silicon and germanium nanostructures were fabricated by the combination of dry etching and vapor-liquid-solid (VLS) mechanism. Gold nanoparticles, about 20 nm in diameter, captured by self-assemble monolayer were adopted as the hard mask for dry etching and catalyst of germanium growth. Reactive ion etching in an inductive coupled plasma chemical vapor deposition (ICPCVD) system was used to fabricate various silicon nanostructures. Instead of CF4, SF6, and SiCl4 gases, hydrogen plasma was used alone as the etching species to construct high-aspect-ratio silicon nanowires. Germanium nanostructures were then fabricated on the surface of silicon nanowires by dry etching and VLS mechanism.

Copper interconnection integration and reliability

A processing sequence to produce a multilevel Cu/polyimide structure which is stable in a corrosive environment is described. Using a combination of dry etching and chemical-mechanical polishing, a fully planarized Cu/polyimide wiring structure was obtained. This technology has been successfully applied to the fabrication of 64 kb complementary metal-oxide-semiconductor static random access memory (CMOS SRAM) chips. Chip functionality was not affected by 12 thermal cycles from 20 to 400 °C. The electromigration activation energy for evaporated Cu, Cu(Mg), Cu(Zr), Cu(Sn) and chemical vapour deposition (CVD) pure Cu was evaluated using a drift velocity technique. The mass transport rates of CVD Cu and evaporated Cu were found to be essentially the same, with an electromigration activation energy of 0.70 ± 0.05 eV. An Mg impurity in Cu enhances the electromigration damage rate in Cu, while Sn and Zr drastically increase the Cu electromigration failure lifetime.