Combination Of Adders Research Articles

Analysis of Efficient 32 Bit Adder Using Tree Grafting Technique

Adder with high efficiency and accuracy is the major requirement for electronic circuit design. Here the optical logic gate based adder circuit is designed for better performance analysis of optical input signals varied with the wavelength. Efficiency of the adder can be improved by increasing the speed of operation, reducing the complexity and power consumption. To maintain the high efficiency with accuracy, a new combination of adder has been proposed and tested in this work. A new adder by combining the logics of Brent Kung, Sklansky and Kogge Stone adders by Tree Grafting Technique (BSKTGT) has been tested along with individual Brent Kung, Sklansky, Kogge Stone, Knowles, Han Carlson and Ladner Fischer adders. All the existing and proposed adders have been designed and tested for efficiency with the help of Cadence platform with 45 nm technology. Efficiency in terms of Size reduction, Power reduction, Power Delay Product (PDP) and accuracy in adding 8 bit, 16 bit and 32 bit values had been tested for all the adders and found that the 32 bit BSKTGT adder performed well in all aspects and have produced better efficiency with the power consumption of 52.512426 μW with 3.16% of power saving over Brent Kung adder, utilised an area of 631.191 with 8.55% reduction over Kogge Stone Adder, has the cell count of 132 which is 10.61% reduction over Brent Kung Adder and PDP value of 122.6695 J, which is 0.46% less than that of the Han Carlson Adder.

Design of Parity Preserving Reversible DIF-FFT using 90nm Technology

Reduction of power consumption is the major goal in modern circuit design. Reversible logic gate do not lose any information & thus have zero power dissipation. In all signal processing applications, the most important computation involved is Fast Fourier Transform (FFT). For the fault tolerance computation parity preserving logic can be used .The authors present an efficient parity preserving reversible DIF-FFT using 90nm technology. The implementation involves the design of DIF-FFT with reversible P2RG along with Fredkin gate over different combinations of adders (Carry look ahead adder (CLA), Carry save adders (CSA), Carry skip adder (CSK) & Ripple carry adder (RCA)) & multipliers (Array Multiplier (AM), Carry Save Multiplier (CM), Parallel Multiplier (PM), Wallace Tree Multiplier (WM)). DIF-FFT Architectures of different combinations were coded using Verilog & the same was simulated by Modelsim 6.3f. Parameters such as Hardware Device utilization & Power analysis were done using Quartus II 9.0 with respect to Stratix II device which works on 90nm technology. It was found that DIF-FFT Architecture designed using CSA & CM uses lesser resource utilization whereas architecture designed using CSA & AM has lesser Power dissipation by 72% & 81% respectively.

Low power and high performance FFT with different radices

<p>FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also considers the precision and the data format to represent constant value such as Q-point. The proposed FFT architectures not only uphold better solutions for low power and high-performance application systems, but also open up a new research lines. This paper demonstrates that radix-2^3 consumes 43% less LUTs and 17% less power consumption, 40% increase of frequency in radix-2^2 in comparison with radix- 2 algorithm for the combination of CSA with modified booth multiplier and the increment of frequency about 19%, 26% less LUTs consumption and 26% less power in Radix-2^2 when compared to radix-4 with various combination of adder and multiplier. In this work we have used Xilinx 14.7 XST for synthesis and the target device used is Spartan6 XC6SLX100. Simulation is carried out in Xilinx ISIM and also performed timing analysis and generated post-place and route.</p>

Comparative Analysis of Noise, Power, Delay and Area of Different Full Adders in 45nm Technology

VLSI Circuit Design is a significant subject for instance like adders and multipliers for the implementation of a various of logic and arithmetic functions likes of basic circuit approach and topology. Full adders like digital signal processors (DSP) architectures and microprocessors are vital elements in the application. Apart from that, the adding of two numbers is main assignment. it's key that determines the overall speed of the critical path lies in the vast majority of these systems like subtraction, multiplication , division , address calculation system as participate in many other activities . So the 1 -bit full adder cells (connective building blocks) is an essential objective of attractive performance. This paper show relative study of high- speed, low-power and low voltage full adder circuits. Our aim is to compare different XOR - XNOR full adder based circuit to and designs a high efficiency adder. We have studied 27 different combinations of adders and studied noise, average power, the ability to delay, utilization of space in 45nm technology.

Elementary limit cycles with application to the testing of digital circuits

Limit cycles in recursive digital filters are normally regarded as undesirable parasitic effects that one tries to minimize. However, one can also regard limit cycles as readily observable (and predictable) patterns of behavior that can be used to verify if a digital circuit is functioning properly. In this letter patterns of simple limit cycles that occur in first-order systems subject to some form of truncation or rounding, that are excited by a constant input, are investigated and classified in accordance with elementary number theory. The simplest of these result in input-output patterns that enable rapid verification of the correct functioning of simple combinations of adders and multipliers. As such they provide a useful method for testing this type of circuit in addition to conventional methods. Necessary and sufficient conditions for the following situations are derived: (i) a unique constant solution; (ii) a limit cycle of period 2 samples and of magnitude equal to m (integer), with m = 1 the most useful case; (iii) multiple constant solutions occurring in simple clusters; (iv) multiple limit cycles of type (ii) encircling a constant solution. Of these, type (ii) provides the most useful results for testing purposes. It is shown how the occurrence or nonoccurrence of limit cycles is related to increments in the value of u. It is also shown that limit cycles of period greater than 2 samples do not exist.

Audio signal translation with no delay elements

Spatially correlated input audio signals are combined in a first combination of adder and subtracter to produce an input summation signal and an input difference signal, which are respectively translated by first and second filter circuits. The transfer function of the first filter circuit describes the relationship between the input summation signal and a summation of output audio signals and the transfer function of the second filter circuit describes the relationship between the input difference signal and a difference between the output audio signals. The translated signals are combined in a second combination of adder and subtracter to produce the output audio signals. Each of the filter circuits is designed with a minimum amount of phase shift which allows elimination of delay elements.