Column Readout Circuit Research Articles

A Reconfigurable Convolution-in-Pixel CMOS Image Sensor Architecture

The separation of the data capture and analysis in modern vision systems has led to a massive amount of data transfer between the end devices and cloud computers, resulting in long latency, slow response, and high power consumption. Efficient hardware architectures are under focused development to enable Artificial Intelligence (AI) at the resource-limited sensing devices. One of the most promising solutions is to enable Processing-in-Pixel (PIP) scheme. However, the conventional schemes suffer from the low fill-factor issue. This paper proposes a PIP based Complementary Metal-Oxide-Semiconductor (CMOS) sensor architecture, which allows convolution operation before the column readout circuit to significantly reduce the overall power consumption while improving the resource utilization of the succeeding deep learning accelerator. The simulation results show that the proposed architecture could support the computing efficiency up to 3.37 TOPS/W at the 8-bit weight configuration, which is four times as high as the conventional schemes after normalization. The transistors required for each pixel are only 3.5T, significantly improving the fill-factor.

Design Improvements on Fast, High-Order, Incremental Sigma-Delta ADCs for Low-Noise Stacked CMOS Image Sensors

Modern CMOS imaging devices are present everywhere, in the form of line, area and depth scanners. These image devices can be used in the automotive field, in industrial applications, in the consumer’s market, and in various medical and scientific areas. Particularly in industrial and scientific applications, the low-light noise performance or the high dynamic-range features are often the cases of interest, combined with low power dissipation and high frame rates. In this sense, the noise floor performance and the power consumption are the focus of this work, given that both are interlinked and play a direct role in the remaining sensor features. It is known that thermal and flicker noise sources are the main contributors to the degradation of the sensor performance, concerning the sensor output image noise. This paper presents an indirect way to reduce both the thermal and the flicker noise contributions by using thin-oxide low voltage supply column readout circuits and fast 3rd order incremental sigma-delta converters with noise shaping capabilities (to provide low noise output digital samples—74 μVrms; 0.7 e−rms; at 105 μV/e−), and thus performing correlated double sampling in a short time (19 μs), while dissipating significant low power (346 μW). Throughout the extensive parametric transistor-level simulations, the readout path produced 1.2% non-linearity, with a competitive saturation capacity (6.5 ke−) pixel. In addition, this paper addresses the readout parallelism as the main point of interest, decoupling resolution from the image noise and the frame rate, at virtually any array resolution. The design and simulations were performed with Virtuoso 6.17 tools (Cadence Design Systems, San Jose, CA, USA) using Spectre models from TS18IS Image Sensor 0.18 µm Process Development Kit (Tower Jazz Semiconductor, Migdal Haemek, Israel).

An improved segmented DAC for column readout circuit correction of large array CMOS image sensor

An improved segmented DAC for column readout circuit correction of large array CMOS image sensor

Column readout circuit with improved offset mismatch and charge sharing for CMOS image sensor

High linearity and low noise column readout chain are two key factors in CMOS image sensor. However, offset mismatch and charge sharing always exist in the conventional column wise readout implementation, even adopting the technology of correlated double sample. A simple column readout circuit with improved offset mismatch and charge sharing for CMOS image sensor is proposed in this paper. Based on the bottom plate sampling and fixed common level method, this novel design can avoid the offset nonuniformity between the two buffers. Also, the single buffer and switched capacitor technique can effectively suppress the charge sharing caused by the varied operating point. The proposed approach is experimentally verified in a 1024 × 1024 prototype chip designed and fabricated in 55 nm low power CMOS process. The measurement results show that the linear range is extended by 20%, the readout noise of bright and dark fields is reduced by 40% and 30% respectively, and the improved photo response nonuniformity is up to 1.16%. Finally, a raw sample image taken by the prototype sensor shows the excellent practical performance.

14-bit column readout circuits with single-to-differential PGA using intentional offset and two-step scaled-reference SAR ADC for CMOS image sensors

High dynamic range (DR) readout circuits with an intentional offset fully differential output correlated double sampling (CDS) programmable gain amplifier (PGA) and a 14-bit differential input range two-step scaled-reference successive approximation register (SAR) analog digital converter (ADC) are proposed in this paper. The PGA is designed to add an intentional offset to prevent the circuits from saturation in the dark–light environment and convert single-ended and unipolar sensor voltages into a differential and bipolar form for a following-up fully differential input range ADC to improve DR of the readout circuits. The SAR ADC composes 7-bit complementary capacitor array to realize 14-bit differential resolution. Scaled reference buffers with self-calibration operation is presented to work in with the SAR ADC. The PGA and ADC work in pipeline mode to increase the frame rate. The 14-bit readout circuits operating at 600 kSps are integrated in a CMOS image sensor (CIS) with 160 × 190 pixel number, 3000 frame/s (fps) and 25 μm × 25 μm pixel pitch for remote sensing. It is verified using 180 nm CMOS process. The measurement results show that the SNR and SNDR of the prototype ADC is 73.90 and 73.01 dB respectively. The referred input noise of the readout circuits is 117 μVrms. A single column readout circuit consumes 2.48 mW under 3.3 V supply voltage. The figure of merit (FoM) of the CIS is 198 μV × nJ.

Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors.

This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS) technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs). This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC). The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median): 0.29 e−rms) when compared with the CMS gain of two (2.4 e−rms), or 16 (1.1 e−rms).

Stripe noise removal for infrared image by minimizing difference between columns

This paper introduces a novel approach to eliminate stripe noise in infrared images. The differences between bias voltages in column readout circuit of uncooled infrared sensors result in strong stripe noise which changes slowly in time. The problem can be solved by estimating the bias of each column of infrared images and correcting infrared images with the estimated biases. The bias estimation is translated into an energy optimization problem in the paper. The optimization aims to minimize difference between neighboring columns of images. Our approach can be processed on a single image, or in a recursive way in order to significantly reduce the computation in one frame time. Our approach is compared to the state-of-the-art the stripe noise removal method using realistic infrared images, and the experimental results show the effectiveness and efficiencies of our proposed approach.

Column readout circuit with dual integration CDS for infrared imagers

A column readout circuit with proposed dual integration CDS for low pattern noise infrared imager is presented. By using an extra integration, the dual integration CDS effectively reduces the level of column and row noise (CN and RN) and column fixed pattern noise (CFPN) in an infrared image. In addition, a time flexible integration technique minimizes the penalty of readout time by a dual operation. Simulation of a 0.18 μm CMOS implementation suggests that CN can be reduced by 68%, RN by 71%, and CFPN by 95% compared with a column readout circuit with conventional CDS.

A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit

A 5.0 G-pixel/s readout circuit for 15.3 mm $\times$ 8.6 mm optical size, 3.7 M-pixel, 1300 fps, and digital output image sensor for industrial applications is presented. With the column parallel ADC, the speed bottleneck is the vertical analog readout. To achieve a 5.0 G-pixel/s readout rate, a high speed column readout circuit is introduced. The novel pixel readout with the slew-enhancement and the time-interleaved correlated double sampling circuit is introduced to increase the readout rate. Besides, the A/D converter with the delay-and-gray code counter and the distributed digital data transfer schemes are innovated in order to reduce the noise interference to the foreground analog signal settling. The 1 horizontal (1H) readout time is 1.0 $\mu$ s.

Development of Highly Sensitive Ion Imager Corresponding to Real-Time Readout Having Single-Ion Detectability

We designed a new type of stacked complementary metal–oxide–semiconductor active pixel sensor (SCAPS) for charged particles with real-time readout and single-ion detection capabilities. Here we present the characteristics of a new imager, SCAPS-II, which implements a newly devised pixel structure of 504×504 pixels for high sensitivity and a noise-reduction mechanism with analog accumulation capabilities inside the column readout circuits. The sensitivity for ions was estimated to be 150 µV/ion under 10 keV Si+ ion irradiation, which is 5 times greater than that of conventional SCAPS. The noise floor was at the 3 ion level without the noise-reduction mechanism at a frame rate of 0.16 s/frame. The noise reduction mechanism reduced the noise to the 1.7 ion level at 0.3 s/frame with 13 samplings. A combination of the noise-reduction mechanism and a multiple-frame-averaging technique achieved a noise level of 0.3 ions. Single-ion detectability was demonstrated using a combination of the noise-reduction mechanism and the multiple-frame-averaging technique that reduced the noise to the 0.3 ion level with 13 samplings, employing an integration circuit and 50-frame averaging at 14.4 s/frame.

Measurement of low-noise column readout circuits for CMOS image sensors

This brief describes the measurement results of high-gain column readout circuits for CMOS image sensors. The measurement results show that the double-stage noise-canceling architecture has better noise performance than that of the single-stage architecture at a first-stage gain of greater than 6. The lowest input-referred noise is measured to be 49 muVrms at a gain of 24

픽셀의 고정 패턴 잡음을 감소시킨 윤곽 검출용 시각칩

When fabricating a vision chip, we should consider the noise problem, such as the fixed pattern noise(FPN) due to the process variation. In this paper, we propose an edge-detection circuit based on biological retina using the offset-free column readout circuit to reduce the FPN occurring in the photo-detector. The offset-free column readout circuit consists of one source follower, one capacitor and five transmission gates. As a result, it is simpler and smaller than a general correlated double sampling(CDS) circuit. A vision chip for edge detection has been designed and fabricated using <TEX>$0.35\;{\mu}m$</TEX> 2-poly 4-metal CMOS technology, and its output characteristics have been investigated.