Column-Parallel Charge Coupled Devices Research Articles

A 4-MHz, 256-Channel Readout ASIC for Column-Parallel CCDs With 78.7-dB Dynamic Range

A 256-channel readout application specific integrated circuit (ASIC) called the very low-noise analog sampling engine (VASE) intended for the readout of column-parallel charge-coupled devices (CP-CCDs), is presented. Each channel uses a charge-sensitive amplifier and a first-order dual-gain sigma-delta analog-to-digital converter (ADC) that act as the front end of an extended counting ADC. The extended counting ADC directly implements correlated multiple-sampling as part of its operation. To reduce the noise due to input capacitance and to ensure a compact camera, the VASE input bonding pads are pitch matched to the CP-CCD to allow chip-to-chip bonding with minimal parasitic capacitance. The chip is designed in a modular way with each 16 input channels sharing a single differential analog output and digital serializer. VASE, with a die area of 38.1 mm2 and fabricated in 180-nm CMOS technology, achieves 22 e− equivalent noise charge (ENC) and a dynamic range of 190 ke− (78.7 dB) at a 4-MHz pixel rate (corresponding to a frame rate of 32 kfps when a $256\times256$ pixel sensor is read out on both sides) while dissipating 10.1 mW per channel. The prototype has been used to successfully image X-ray diffraction at a soft X-ray synchrotron.

Multiplexed Oversampling Digitizer in 65 nm CMOS for Column-Parallel CCD Readout

A digitizer designed to read out column-parallel charge-coupled devices used for high-speed X-ray imaging is presented. The digitizer is included as part of the High-Speed Image Preprocessor with Oversampling integrated circuit. The digitizer module comprises a multiplexed, oversampling, 12-bit, 80 MS/s pipelined analog-to-digital converter and a bank of four fast-settling sample-and-hold amplifiers to instrument four analog channels. The analog-to-digital converter multiplexes and oversamples to reduce its area to allow integration that is pitch-matched to the columns of the imager. Novel design techniques are used to enable oversampling and multiplexing with a reduced power penalty. The analog-to-digital converter exhibits 188 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu$</tex></formula> V-rms noise which is less than 1 LSB at a 12-bit level. The prototype is implemented in a commercially available 65-nm CMOS process. The digitizer will be applied to the development of a proof-of-principle 2D, 10 Gigapixel/s X-ray detector.

Modeling of Radiation Hardness of a CCD with High-Speed Column Parallel Readout

Charge Coupled Devices (CCDs) have been successfully used in several high energy physics experiments over the past two decades. Their high spatial resolution and thin sensitive layers make them an excellent tool for studying short-lived particles. The Linear Collider Flavour Identification (LCFI) collaboration is developing Column-Parallel CCDs (CPCCDs) for the vertex detector of a future Linear Collider. The CPCCDs can be read out many times faster than standard CCDs, significantly increasing their operating speed. An Analytic Model has been developed for the determination of the charge transfer inefficiency (CTI) of a CPCCD. The CTI values determined with the Analytic Model agree largely with those from a full TCAD simulation. The Analytic Model allows efficient study of the variation of the CTI on parameters like readout frequency, operating temperature and occupancy.

Comparison of Measurements of Charge Transfer Inefficiencies in a CCD With High-Speed Column Parallel Readout

Charge Coupled Devices (CCDs) have been successfully used in several high energy physics experiments over the past two decades. Their high spatial resolution and thin sensitive layers make them an excellent tool for studying short-lived particles. The Linear Collider Flavour Identification (LCFI) Collaboration has been developing Column-Parallel CCDs for the vertex detector of a future Linear Collider which can be read out many times faster than standard CCDs. The most recent studies are of devices designed to reduce both the CCD's intergate capacitance and the clock voltages necessary to drive it. A comparative study of measured Charge Transfer Inefficiency values between our previous and new results for a range of operating temperatures is presented.

Direct electron detection for TEM with column parallel CCD

Step improvements in electron detectors are needed for transmission electron microscopes (TEM) to take full advantage of latest developments in electron optics and electron sources. This work presents beam tests performed with column parallel charge-coupled devices (CPCCD) and discusses measured cluster properties. Excellent signal-to-noise ratio is found, demonstrating that CPCCD are well suited for TEM. Large variations in cluster-integrated intensity and size are observed, attributed to the strong scattering of 120–200 keV electrons in silicon. Spatial momentum analysis of clusters reveals strong asymmetry indicating that position resolution could be limited for certain cluster shapes.

Modeling of Charge Transfer Inefficiency in a CCD With High-Speed Column Parallel Readout

Charge Coupled Devices (CCDs) have been successfully used in several high energy physics experiments over the past two decades. Their high spatial resolution and thin sensitive layers make them an excellent tool for studying short-lived particles. The Linear Collider Flavour Identification (LCFI) collaboration is developing Column-Parallel CCDs (CPCCDs) for the vertex detector of a future Linear Collider. The CPCCDs can be read out many times faster than standard CCDs, significantly increasing their operating speed. An Analytic Model has been developed for the determination of the charge transfer inefficiency (CTI) of a CPCCD. The CTI values determined with the Analytic Model agree largely with those from a full TCAD simulation. The Analytic Model allows efficient study of the variation of the CTI on parameters like readout frequency, operating temperature and occupancy.

Measurements of Charge Transfer Inefficiency in a CCD With High-Speed Column Parallel Readout

Charge Coupled Devices (CCDs) have been successfully used in several high energy physics experiments over the past two decades. Their high spatial resolution and thin sensitive layers make them an excellent tool for studying short-lived particles. The Linear Collider Flavour Identification (LCFI) collaboration is developing Column-Parallel CCDs (CPCCDs) for the vertex detector of a future Linear Collider. The CPCCDs can be read out many times faster than standard CCDs, significantly increasing their operating speed. A test stand for measuring the charge transfer inefficiency (CTI) of a prototype CPCCD has been set up. Studies of the CTI have been performed at a range of readout frequencies and operating temperatures.

Radiation hardness studies in a CCD with high-speed column parallel readout

Charge Coupled Devices (CCDs) have been successfully used in several high energy physics experiments over the past two decades. Their high spatial resolution and thin sensitive layers make them an excellent tool for studying short-lived particles. The Linear Collider Flavour Identification (LCFI) collaboration is developing Column-Parallel CCDs (CPCCDs) for the vertex detector of the International Linear Collider (ILC). The CPCCDs can be read out many times faster than standard CCDs, significantly increasing their operating speed. The results of detailed simulations of the charge transfer inefficiency (CTI) of a prototype CPCCD including the variation of model parameters are reported. The effects of bulk radiation damage on the CTI of a CPCCD are studied by simulating the effects of two electron trap levels, 0.17 and 0.44 eV, at different concentrations and operating temperatures. The dependence of the CTI on different occupancy levels (percentage of hit pixels) and readout frequencies is also studied. The optimal operating temperature for the CPCCD, where the effects of the charge trapping are at a minimum, is found to be about 230 K for the range of readout speeds proposed for the ILC. The results of the full simulation have been compared with an analytic model.

Simulation of the charge transfer inefficiency of column parallel CCDs

Charge-Coupled Devices (CCDs) have been successfully used in several high-energy physics experiments over the past two decades. Their high spatial resolution and thin sensitive layer make them an excellent tool for studying short-lived particles. The Linear Collider Flavour Identification (LCFI) collaboration is developing Column Parallel CCDs (CPCCDs) for the vertex detector of the International Linear Collider (ILC). The CPCCDs can be read out many times faster than standard CCDs, significantly increasing their operating speed. The results of detailed simulations of the Charge Transfer Inefficiency (CTI) of a prototype CPCCD chip are reported. The effects of the radiation damage on the CTI of a Si-based CCD particle detector are studied by simulating the effects of two electron trap levels Ec-0.17 and Ec-0.44 eV at different concentrations and operating temperatures. The dependence of the CTI on different occupancy levels (percentage of hit pixels) and readout frequencies is also studied. The optimal operating temperature—where the effects of the trapping are at a minimum—is found to be ∼230 K for the range of readout speeds proposed for the ILC.

CCD-based vertex detector for ILC

Charge Coupled Devices (CCDs) have been successfully used in several high-energy physics experiments over the last 20 years. Their small pixel size and excellent precision provide a superb tool for studying of short-lived particles and understanding the nature at fundamental level. Over the last few years the Linear Collider Flavour Identification (LCFI) collaboration has developed Column-Parallel CCDs (CPCCD) and CMOS readout chips, to be used for the vertex detector at the International Linear Collider (ILC). The CPCCDs are very fast devices capable of satisfying the challenging requirements imposed by the beam structure of the superconducting accelerator. The first set of prototype devices have been successfully designed, manufactured and tested, with second generation chips on the way. Another idea for CCD-based device, the In-situ Storage Image Sensor (ISIS) is also under development and the first prototype has been manufactured.

CCD developments for particle colliders

Charge Coupled Devices (CCDs) have been successfully used in several high-energy physics experiments over the last 20 years. Their small pixel size and excellent precision provide superb tool for studying of short-lived particles and understanding the nature at fundamental level. Over the last years the Linear Collider Flavour Identification (LCFI) collaboration has developed Column-Parallel CCDs (CPCCD) and CMOS readout chips to be used for the vertex detector at the International Linear Collider (ILC). The CPCCDs are very fast devices capable of satisfying the challenging requirements imposed by the beam structure of the superconducting accelerator. First set of prototype devices have been designed, manufactured and successfully tested, with second-generation chips on the way. Another idea for CCD-based device, the In-situ Storage Image Sensor (ISIS) is also under development and the first prototype is in production.