Column-parallel Analog-to-digital Converter Research Articles

A Comprehensive Methodology for Optimizing Read-Out Timing and Reference DAC Offset in High Frame Rate Image Sensing Systems.

This paper presents a comprehensive timing optimization methodology for power-efficient high-resolution image sensors with column-parallel single-slope analog-to-digital converters (ADCs). The aim of the method is to optimize the read-out timing for each period in the image sensor's operation, while considering various factors such as ADC decision time, slew rate, and settling time. By adjusting the ramp reference offset and optimizing the amplifier bandwidth of the comparator, the proposed methodology minimizes the power consumption of the amplifier array, which is one of the most power-hungry circuits in the system, while maintaining a small color linearity error and ensuring optimal performance. To demonstrate the effectiveness of the proposed method, a power-efficient 108 MP 3-D stacked CMOS image sensor with a 10-bit column-parallel single-slope ADC array was implemented and verified. The image sensor achieved a random noise of 1.4 e-rms, a column fixed-pattern noise of 66 ppm at an analog gain of 16, and a remarkable figure-of-merit (FoM) of 0.71 e-·nJ. The sensor utilized a one-row read-out time of 6.9 µs, an amplifier bandwidth of 1.1 MHz, and a reference digital-to-analog converter (DAC) offset of 512 LSB. This timing optimization methodology enhances energy efficiency in high-resolution image sensors, enabling higher frame rates and improved system performance. It could be adapted for various imaging applications requiring optimized performance and reduced power consumption, making it a valuable tool for designers aiming to achieve optimal performance in power-sensitive applications.

2μs row time 12-bit column-parallel single slope ADC for high-speed CMOS image sensor

To improve the conversion speed of single-slope (SS) analog-to-digital converter (ADC) for high frame rate CMOS image sensor, a cycle time-to-digital converter (TDC)-based readout technique is proposed, which optimizes the quantization method. And the proposed SS ADC prioritizes the quantization of the most significant bit (MSB), aiming to shorten the search range of the slope and greatly improve the quantization speed while ensuring accuracy. Furthermore, the proposed scheme is reversible to operate the conventional SS ADC algorithm, thus it preserves the structural advantages of the SS ADC. The proposed SS ADC is designed and simulated with 0.11-μm process. The simulation results show that the row time of SS ADC is 2 μs and the resolution is 500 ps, which greatly improves the quantization speed while ensuring power consumption and accuracy. The FoM is 182.6 fJ/step, which is a 7.1% improvement compared to other TDC-based SS ADCs. The proposed SS ADC becomes more effective as the bit-depth of the ADC increases.

A column-parallel 1-bit ADC with threshold offset reduction technique for single-bit quanta image sensor

This paper presents a column-parallel 1-bit analog-to-digital converter (ADC) with threshold offset reduction technique, which aims to reduce the bit error rate (BER) of single-bit quanta image sensor (QIS). The fixed offset of the differential charge transfer amplifier (DCTA) and the fixed compensation offset of the calibrated dynamic latch (CD-latch) comparator are eliminated by two coupling capacitors. Additionally, an improved 3-stage DCTA with low gain error is designed to further suppress the fixed residual offset of the CD-latch. The proposed circuit is implemented by a 110 nm CMOS process. Post-simulation results show that the proposed 1-bit ADC achieves a threshold offset of 32.6 μV at 4 MSa/s sampling rate and 500 μV quantization threshold. Compared with the conventional structure, the random noise of the proposed 1-bit ADC remains almost unaltered. Meanwhile, its threshold offset is lowered by 153.6 μV, making the model BER and circuit BER of the column-level circuit reduce from 2.42% to 0.21% and 2.29%–0.26%, respectively.

11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors

A first-step half-reference ramping (FHR) readout scheme is presented in this study for high frame rate CMOS image sensors (CISs). The proposed readout scheme enhances the conversion speed of a single-slope (SS) analog-to-digital converter (ADC) by applying a binary-weighted searching algorithm at the first A/D conversion attempt. By effectively reducing the reference signal range, the proposed FHR readout scheme can reduce the number of A/D conversion steps in the SS ADC while maintaining the ADC performance. Furthermore, the proposed scheme is reversible to operate the conventional SS ADC algorithm, thus it preserves the structural advantages of the SS ADC. The proposed FHR scheme becomes more effective as the bit-depth of the ADC increases. A prototype CIS with a column-parallel 11-bit SS ADC was fabricated in a 0.11- $\mu \text{m}$ 1P4M CIS process with a 2.9- $\mu \text{m}$ pixel pitch. A maximum frame rate of 570 frames/s was achieved with a $1024\times240$ pixel resolution, corresponding to a 140.08 Mp/s pixel rate. Total power consumption was 57.2 mW under 2.8 V for pixel readout and 1.8 V for readout circuitry. When compared with the conventional 11-bit SS ADC, the proposed FHR scheme shortens the total A/D conversion time by 38.4%. The prototype CIS demonstrated the figure of merits (FoM) of 0.84 $\text{e}^{-}\cdot $ nJ and 0.41 $\text{e}^{-}\cdot $ nJ/step.

Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current

This paper presents a 9-bit, 2-stage cyclic analog to digital converter (ADC) with a variable bias current control circuitry to reduce its power dissipation. Each stage outputs a three-bit digital word and the circuit requires four subcycles to perform a whole conversion. Since the accuracy required is higher in the first stage and first subcycle and decreases in subsequent cycles, the bias current of each operational transconductance amplifier is regulated depending on the subcycle of the conversion process. The resolution and sampling frequency of the converter make it suitable to be integrated with 8-bit CMOS imagers with column-parallel ADC architectures. The ADC has been designed using a 1.2 V 110 nm CMOS technology and the circuit consumes 27.9 µW at a sampling rate of 500 kS/s. At this sampling rate and at a 32 kHz input frequency, the circuit achieves 56 dB of SNDR and 9 bit ENOB. The Figure of Merit is 109 fJ/step.

Energy-Efficient Motion-Triggered IoT CMOS Image Sensor With Capacitor Array-Assisted Charge-Injection SAR ADC

We propose a low-power image sensor with a motion-based triggering feature for the Internet of Things (IoT) applications. The sensor supports the near-pixel [within analog-to-digital converter (ADC)] motion-detection mode run on a heavily subsampled frame (32 $\times $ 20 pixels, while consuming only 1.7 $\mu \text{J}$ /frame) to trigger full-array capture only when a significant change has happened in the scene. Also, to maximize energy efficiency and image quality of the sensor, we propose a column-parallel capacitor array-assisted charge-injection SAR ADC that achieves 10b operation with readout noise of 226 $\mu V_{\text {rms}}$ , which can be lowered to 104 $\mu V_{\text {rms}}$ using multiple sampling. The ADC is highly energy efficient with best-in-class energy consumption of 63.6 pJ/frame/pixel and ADC Figure of Merit (FoM) of 14.4 $\mu V_{\text {rms}}\cdot $ nJ in full-array capture mode.

A 10 bit Fully Differential Dual Slope Analog-to-digital Converter for Time Delay Integration CMOS Image Sensors

A 10 bit fully differential dual slope Analog-to-Digital Converter (ADC) for Time Delay Integration (TDI) CMOS image sensors is realized based on column-parallel single-slope ADC. Top plates of the two capacitors are used for sampling differential inputs, and the bottom plates are connected to ramp generator for conversion. Current steering is used to generate the rising and falling ramp with the same step voltage simultaneously. The proposed ADC is fabricated in SMIC 0.18 μm CMOS process. Simulated spurious free dynamic range and effective number of bits are 87.92 dB and 9.84 bit with the input frequency of 1.32 kHz at 19.49 kS/s sampling rate, respectively. Measured results show that the ADC has a differential nonlinearity of –0.7/+0.6 LSB and integral nonlinearity of –2.6/+2.1 LSB.

A 14-bit column-parallel two-step SA ADC with digital calibration based on scaled references and redundancy for CMOS image sensors

A 14-bit column-parallel two-step successive approximation (SA) analog-to-digital converter (ADC) with digital calibration based on scaled references and redundancy for CMOS image sensors is presented. A 7-bit area-efficient non-binary capacitor array whose total number is same as the 6-bit one is used to meet the dimension constraints imposed by the pixel pitch of 25 μm in the CMOS image sensor. In each conversion period, 14-bit resolution is realized by 16-times comparison which provides redundancy for calibration. Capacitor mismatch and scaled-reference error both deviate the weight of each bit from its designed value. An off-chip digital calibration method based on statistics is adopted to extract the fabricated weight of each bit in the SA ADC. A tri-level switching scheme is employed for the most 8 significant times comparison to reduce switching power of the capacitor array of the SA ADC. The proposed SA ADC is implemented by using 180 nm CIS process and measured at 1 MS/s. The area of the SA ADC is 1637 × 50 μm2. It consumes 78.47 μA under 3.3 V supply voltage. The INL is improved from + 21/− 21 to + 2.3/− 2.5 LSB, SFDR from 73.56 to 85.17 dB and ENOB from 9.57 to 11.15 bit after calibration in the presence of capacitor mismatch and scaled reference errors. The figure of merit of the ADC is 118 fJ/Conv.-step.

A Compressive Sensing-Based CMOS Image Sensor With Second-Order $\Sigma \Delta$ ADCs

This paper presents a new analog-to-digital conversion scheme for a second-order $\Sigma \Delta $ incremental analog to digital converter (ADC) that can be employed in a compressive sensing (CS)-based CMOS image sensor (CIS) as a column-parallel ADC. The conversion scheme removes image distortion from a reconstructed image by making the ADC output codes represent an average of the ADC inputs. In addition, a new multiplexing scheme implementing a compressive sensing matrix helps to reduce hardware complexity and control compression ratio without hardware modifications. A $160\times 160$ pixel CS-based CIS fabricated in $0.11~\mu \text{m}$ CIS process successfully demonstrates the proposed schemes.

A Two-Step Prediction ADC Architecture for Integrated Low Power Image Sensors

This paper presents a two-step prediction method for the design of low-power column-parallel analog-to-digital converters (ADC) in CMOS image sensors. The proposed prediction method takes advantage of the spatial likelihood of natural scenes, which shows strong correlations between neighboring pixels in the image. Based on this property, the proposed method predicts the MSBs of the selected pixel using quantization results of the neighboring pixels in the previous row, which enables a significant power reduction of the A/D conversions. The simulation results show that up to 20~30% power saving can be achieved for most natural scenes. A 384 × 256-pixel prototype chip was fabricated using a 0.35 μm CMOS technology with a pixel footprint of 15 μm × 15 μm. The fill factor is 49%. 10-bit successive approximation register (SAR) ADCs are used in the column-parallel ADC array.

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor.

The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

A Column-Parallel Inverter-Based Cyclic ADC for CMOS Image Sensor With Capacitance and Clock Scaling

This paper presents a low-power column-parallel inverter-based cyclic analog-to-digital converter (ADC) for CMOS image sensor readout circuit. By partially floating the capacitors inside the multiply digital-analog-converter during the least significant bit (LSB) quantization, the amplifier load capacitance could be significantly scaled down, which allows much higher settling speed and shorter cycle period. Since the signal-to-noise ratio for LSB cycle is relaxed due to the residual amplification, the proposed capacitance scaling only contributes ignorable input-referred quantization noise. Using the proposed techniques, a cyclic ADC can operate under 50% power consumption without suffering conversion rate, noise performance, and linearity. A 12-b quantization resolution test chip is fabricated using the TSMC 0.18-μm technology with 110 column-parallel ADC channels and 10.08-μm × 750-μm column pitch. The 3.5/-2 LSBs integral nonlinearity and 10.1-b effective-number-of-bit are measured under 2-μs sampling rate with 120-μW power consumption per channel.

Always-On CMOS Image Sensor for Mobile and Wearable Devices

This paper presents a low-power always-on image sensor for mobile and wearable device applications. The sensor continuously captures images for smart sensing, such as face detection, eye tracking, and gesture recognition, and it provides high-resolution images for capturing pictures with a unified sensor. The sensor employs a switchable dual mode: always-on (AO) mode with low power consumption and photo-shooting (PS) mode with high signal-to-noise ratio. For dual-mode operation with high energy efficiency, we implemented dynamic voltage scaling that provides 0.9 V analog–digital supply voltage for the AO mode and 3.3 V analog–1.8 V digital supply voltage for the PS mode. For low-voltage operation in the AO mode, a conventional four-transistor pixel operates as a charge-shared pixel. In order to suppress power consumption and frequency in conventional single-slope analog-to-digital converters (ADC), two neighboring column-parallel ADCs are reconfigured to one successive-approximation ADC for low-voltage and low-frequency operation in the AO mode with negligible area overhead. The fabricated 640 $\,\times\,$ 480 pixel prototype sensor operates at 45.5 $\mu$ W (at 15 fps, 320 $\,\times\,$ 240) in the AO mode, which significantly extends battery life when performing always-on sensing.

A Low-Power CMOS Image Sensor With Area-Efficient 14-bit Two-Step SA ADCs Using Pseudomultiple Sampling Method

This brief presents a low-power CMOS image sensor with 14-bit column-parallel two-step (TS) successive approximation (SA) analog-to-digital converters (ADCs). The proposed TS SA ADC adopts a pseudomultiple sampling method to reduce the power consumption and the area. For implementing the 14-bit ADC, it only uses a capacitor digital-to-analog converter of 6 bits rather than 14 bits. The multiple sampling also suppresses the noise of a pixel and a column-parallel ADC. The image sensor is fabricated by using the 0.13-μm CMOS process. The measurement results show that the temporal noise is 82.7 μVrms, and the power consumption is 55.1 μW for one column ADC with a programmable gain amplifier. With the digital correlated double sampling and the TS calibration method, the proposed ADC achieves the column fixed-pattern noise of 0.98 LSB and a differential nonlinearity of +0.99/-0.90 LSB.

A 10-bit ratio-independent cyclic ADC with offset canceling for a CMOS image sensor

A 10-bit ratio-independent switch-capacitor (SC) cyclic analog-to-digital converter (ADC) with offset canceling for a CMOS image sensor is presented. The proposed ADC completes an N-bit conversion in 1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversion characteristic of the proposed cyclic ADC is inherently insensitive both to capacitor ratio and to amplifier offset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18-μm one-poly four-metal CMOS technology. The measured results indicate that the ADC has a signal-to-noise and distortion ratio (SNDR) of 53.6 dB and a DNL of +0:12/−0:14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 μW with a 1.8 V supply, and its area is 0.03 × 0.8 mm2.

A Low-Power Pilot-DAC Based Column Parallel 8b SAR ADC With Forward Error Correction for CMOS Image Sensors

Successive-Approximation-Register (SAR) Analog- to-Digital Converters (ADC) have been shown to be suitable for low-power applications at aggressively scaled CMOS technology nodes. This is desirable for many mobile and portable applications. Unfortunately, SAR ADCs tend to incur significant area cost and reference loading due to the large capacitor array used in its Digital-to-Analog Converter (DAC). This has traditionally made it difficult to implement large numbers of SAR ADC in parallel. This paper describes a compact 8b SAR ADC measuring only 348 μm×7 μm. It uses a new pilot-DAC (pDAC) technique to reduce the power consumption in its capacitor array; moreover, the accuracy of the pDAC scheme is protected by a novel mixed-signal Forward Error Correction (FEC) algorithm with minimal circuit overhead. Any DAC error made during pDAC operation can be recovered later by an additional switching phase. Prototype measurements in 0.18 μm technology shows that the DAC's figure-of-merit (FoM) is reduced from 61.3 fJ/step to 39.8 fJ/step by adopting pDAC switching with no apparent deterioration in Fixed-Pattern Noise (FPN) and thermal noise.

A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors

This paper presents a high-speed column-parallel cyclic analog-to-digital converter (ADC) for a CMOS image sensor. A correlated double sampling (CDS) circuit is integrated in the ADC, which avoids a stand-alone CDS circuit block. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.02 mm2 was implemented in a 0.13 μm CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively. The power consumption from 3.3 V supply is only 0.66 mW. An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels. The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.

CMOS Imaging Devices for New Markets of Vision Systems

This paper reviews and discusses devices, circuits, and signal processing techniques for CMOS imaging SoC's based on column-parallel processing architecture. The pinned photodiode technology improves the noise characteristics at the device level to be comparable to CCD image sensors and as a result, low-noise design in CMOS image sensors has been shifted to the reduction of noise at the circuit level. Techniques for reducing the circuit noise are discussed. The performance of the imaging SoC's greatly depends on that of the analog-to-digital converter (ADC) used at the column. Three possible architectures of the column-parallel ADC are reviewed and their advantage and disadvantage are discussed. Finally, a few applications of the device and circuit techniques and the column-parallel processing architecture are described.