Column Driver Research Articles

A fully non-linear column driver with a compact 12-bit DAC for LEDoS displays

A fully non-linear column driver with a compact 12-bit DAC for LEDoS displays

A 10-Bit 20 Channel LCD Column Driver Using Compact DAC

A 20-channel liquid crystal display (LCD) driver architecture is implemented with [Formula: see text]m CMOS technology. This work presents a novel design of 10-bit compact and high-resolution two-stage DAC to improve the linearity and uniformity of each channel performance. A complete column driver, including a compact DAC, low power buffer, global R-string and multiplexing circuit design, is implemented, and the layout of this 20-channel, 10-bit LCD driver is generated using [Formula: see text]m CMOS technology. All the circuit blocks of the proposed LCD column driver were simulated using the EDA tool HSPICE and layout generation by Laker. This work also realizes a high-performance class AB operational amplifier with a gain of 140[Formula: see text]dB for the proposed LCD driver. The 10-bit compact LCD driver has a 1.4 mV LSB and an output voltage of 1.7 V is achieved for the input range of 0.25–1.7[Formula: see text]V. The compact DAC voltage selector with decoder in this design uses fewer switches in comparison to conventional tree-type RDAC, occupying a smaller chip area with fast response. The proposed design is sufficiently robust for high-color depth and resolution LCD driver applications. The experimental results exhibit maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.065 LSB and −0.12 LSB, respectively. The one channel area is [Formula: see text]m and the settling time is [Formula: see text]s for the [Formula: see text] and 20[Formula: see text]pF driving load.

An intelligent soil-cement mixing column driver

Conventional soil–cement columns fail to fully consider the layered structure of foundation soil, resulting in cement waste. Owing to the concealment of the installation site, soil–cement mixing column installation is labor-intensive, and its quality is considerably affected by the skills and experience of the laborers and operators. In this study, soil–cement mixing column installation technology and quality control were investigated by improving the automation and intelligent ability of installation equipment based on the Internet of Things (IoT) technology. An intelligent soil–cement mixing column driver was developed. Field test and engineering application results showed that frequency grouting, installation quality assessment, and on-site and remote monitoring can be implemented. The intelligent soil–cement mixing column driver improved the installation capacity and quality, reduced the cost, and simplified the construction management. The intelligent soil–cement mixing column driver has great potential for engineering applications and development. In the future, a wider range of applications and further intelligent upgrades will be investigated.

A Low-Power CMOS Image Sensor With Multiple-Column-Parallel Readout Structure

This paper presents a low-power multiple-column-parallel (MCP) readout CMOS image sensor (CIS) in terms of its structural features. Because each column in an MCP unit performs analog-to-digital (A/D) conversion sequentially, the columns have their own operating periods before and after A/D conversion. Upon completion of A/D conversion in each column, a local bias control (LBC) scheme is applied using a bias circuit of a pixel source follower (SF) to minimize power consumption. In this study, the effectiveness of the proposed LBC scheme is verified for the MCP readout structure. Through simple modification of a column-biasing circuit, the prototype MCP readout CIS achieved significant power savings, which shows its applicability to low-power CIS applications. The prototype CIS was implemented using a 1P6M 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process. A maximum frame rate of 430 fps was achieved while consuming 2.38 mW of power. Compared to a conventional column driver, the proposed LBC scheme reduces the total power consumption by 29.4%, which is an overall power savings of 15%. The prototype CIS also demonstrated figures of merit of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$119.1 ~\mu \text{V}\cdot $ </tex-math></inline-formula> nJ and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8 ~\mu \text{V}_{\mathrm{ rms}}$ </tex-math></inline-formula> /kHz.

High-Speed Column Driver IC Having Buffer Amplifier with Embedded Isolation Switch and Compact Adaptive Biasing for Flat-Panel Displays

A high-speed column driver IC with an area-efficient high-slew-rate buffer amplifier is proposed for use in a large-sized, high-resolution TFT-LCD panel application. In the proposed architecture, explicit isolation switches have been embedded into the buffer amplifier resulting in a fast settling response. The amplifier also has a structure that adjusts the tail current of the input stage using a very compact adaptive biasing. The proposed column driver IC, having the proposed buffer amplifier for driving a 55-inch 4K ultra-high-definition (UHD) TV panel, was fabricated in a 0.18-μm 1.8-V low-voltage, 1.2-μm 9-V medium-voltage, and 1.6-μm 18-V high-voltage CMOS process. The performance evaluation results indicated that 90% and 99.9% falling settling times were improved from 1.947 µs to 0.710 µs (63.5% improvement) and 4.131 µs to 2.406 µs (41.7% improvement), respectively. They also indicated that the layout size of the proposed buffer amplifier was reduced from 5580 μm2 to 4402 μm2 (21.1% reduction).

High-Speed Rail-to-Rail Class-AB Buffer Amplifier with Compact, Adaptive Biasing for FPD Applications

A high-slew-rate, low-power, CMOS, rail-to-rail buffer amplifier for large flat-panel-display (FPD) applications is proposed. The major circuit of the output buffer is a rail-to-rail, folded-cascode, class-AB amplifier which can control the tail current source using a compact, novel, adaptive biasing scheme. The proposed output buffer amplifier enhances the slew rate throughout the entire rail-to-rail input signal range. To obtain a high slew rate and low power consumption without increasing the static current, the tail current source of the adaptive biasing generates extra current during the transition time of the output buffer amplifier. A column driver IC incorporating the proposed buffer amplifier was fabricated in a 1.6-μm 18-V CMOS technology, whose evaluation results indicated that the static current was reduced by up to 39.2% when providing an identical settling time. The proposed amplifier also achieved up to 49.1% (90% falling) and 19.9 % (99.9% falling) improvements in terms of settling time for almost the same static current drawn and active area occupied.

A Low-Area and Fully Nonlinear 10-Bit Column Driver With Low-Voltage DAC and Switched-Capacitor Amplifier for Active-Matrix Displays

To reduce the circuit area and support a 10-bit fully nonlinear gamma correction, a new column driver architecture constructed with a 10-bit one-stage low-voltage resistor string digital-to-analog converter (RDAC) (LVDAC) and a switched-capacitor amplifier (SC-AMP) is proposed. Because the LVDAC is implemented with low-voltage (LV) MOSFETs instead of high-voltage (HV) MOSFETs, the circuit area is drastically reduced. In addition, there is no need to use level shifters that must be used in the traditional column driver between the LV logic circuit and the HV DAC, thus further decreasing the circuit area. By utilizing a one-stage DAC architecture, the effective bit resolution of nonlinear gamma correction can be increased compared with previous two-stage DACs, in which the output voltages of the coarse DAC are interpolated. The output voltage of LVDAC is amplified by SC-AMP to reach the requisite HV to drive the display panel. In designing the SC-AMP, the effects of non-idealities, such as random offset voltage, capacitance mismatch, parasitic capacitance, and switching error are quantitatively analyzed, and circuit techniques to suppress the effects are presented. The proposed column driver was fabricated using a 90-nm CMOS process. The circuit area of the proposed 10-bit column driver is only 69.0% of that of the conventional 8-bit column driver because the conventional 8-bit HV RDAC (HVDAC) using 5-V MOSFETs is replaced by the proposed 10-bit LVDAC using 1.2-V MOSFETs, along with the SC-AMP with a gain of four to support the 5-V output voltage range. The measurement results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.2/-0.18 and +0.42/-0.06 LSB, respectively, with an LSB voltage of 4.5 mV. The measured maximum deviation of voltage outputs (DVOs) between 50 channels is 7.9 mV.

An Area-Efficient 10-Bit Buffer-Reused DAC for AMOLED Column Driver ICs

In this paper, we proposed an area-efficient 10-bit digital-to-analog converter (DAC) with buffer-reusing method to dramatically relief the severe area exploding issue in high-definition active-matrix organic light-emitting diode (AMOLED) driver integrated circuits (ICs). In our design, we implement the functionalities of a large number of switches and capacitors in conventional DAC by a compact internal buffer. Furthermore, we minimize the buffer capacity requirement by elaborately reusing the indispensable output buffer in the typical column driver. In this way, we can cut down nearly a half of the decoder-switches and simultaneously reduce the capacitor size from 8 C to 3 C without designing an intricate and power-consuming amplifier separately. A prototype 6-channel column driver employing the proposed buffer-reused DAC was fabricated by 0.35 μm 2P3M BCD (Bipolar, CMOS, DMOS) process and its effective layout area per channel is 0.0429 mm2, which is 42.8% smaller than that of the conventional 10-bit R-C DAC. Besides, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.514 LSB/0.631 LSB, respectively and the maximum value of inter-channel deviation voltage output (DVO) is 3.25 mV. The settling time within 5.6 μs is readily achieved under 1.5 kΩ-resistance and 100 pF-capacitance load. Measurement results indicate that the proposed buffer-reused DAC can successfully minimize the die area while maintaining other required performances.

A 10-bit 1026-Channel Column Driver IC With Partially Segmented Piecewise Linear Digital-to-Analog Converters for UHD TFT-LCDs With One Billion Color Display

A 10-bit 1026-channel column driver IC with partially segmented piecewise linear digital-to-analog converters (DACs) was designed, simulated, and prototyped. This device is intended to improve the color depth of ultra-high-definition thin-film transistor liquid-crystal displays. The proposed column driver can output a precise gamma-corrected transfer curve without any loss of effective bit resolution. The overall chip area of the driver IC is minimized by including an area-efficient two-voltage selector, a 2-to-4 decoder embedded level shifter, and a DAC-embedded gm-modulation operational amplifier with linearity-enhanced differential pairs. A maximum inter-chip deviation voltage of output (DVO) of 16 mV was measured from five of the proposed column-driver ICs. The die dimensions of the 1026-channel column driver IC are of only 18.14 mm × 1.2 mm. The maximum settling time of the prototype is 5.6 μs when driving a load with 5-kΩ resistance and 300-pF capacitance within 10-mV tolerance of the final voltage.

Area-efficient Ramp Signal-based Column Driving Technique for AMOLED Panels

This work proposes a ramp signal-based column driving technique to maximize the area efficiency of the column driver integrated circuit (IC) for high-resolution active-matrix organic light emitting diodes (AMOLED) panels. The proposed column driving technique replaces the 2SUPn/SUP reference voltages coming from the conventional n-bit resistor digital-to-analog converters (RDAC) with a single ramp signal, thereby reducing the area of the column driver IC by 44.3%. A weighted two-step interpolation structure, composed of the first-stage 6-bit ramp signal and the second-stage 2-bit amplifier DAC, reduces the required operation speed of the ramp signal under a limited 1-horizontal (1-H) time, while processing 8-bit image signals. The performance of the proposed column driving technique is verified with a 96-channel prototype IC fabricated in a 0.18 μm CMOS process. The deviation of voltage output (DVO) of the prototype IC are within ±6 mV, and the unit channel area is 4200 μ㎡.

A 10-bit Two-Stage R-DAC With Isolating Source Followers for TFT-LCD and AMOLED Column-Driver ICs

This paper proposes a 10-bit two-stage resistor string digital-to-analog converter (R-DAC) architecture with source followers to isolate parallel-connected resistor strings, with a dc-offset compensation scheme to compensate for the offset voltages of the source followers. To compensate for these offset voltages, another source follower is inserted in the feedback loop of the buffer amplifier. Two prototypes of a 24-channel column driver were fabricated using the 0.18-μm CMOS technology; the worst differential nonlinearity and integral nonlinearity through a one-voltage selection scheme were 0.6 and 0.77 LSB, respectively, and those through a two-voltage selection scheme were 0.4 and 0.52 LSB, respectively. The proposed 10-bit two-stage R-DACs with one-/two-voltage selection schemes occupy only 57%/60% of the area of a conventional 8-bit R-DAC using the same technology.

Survey on Single Stage Amplifiers for Column Drivers in Active Matrix LCD Panels Leading to a Highly Linear Rail-to-Rail Robust Amplifier

This paper reviews single stage amplifiers identified in the literature as well as presents a new structure single stage highly linear rail-to-rail amplifier intended for column drivers in Active Matrix Liquid Crystal Display (AMLCD). The new proposed amplifier is based on applying current splitting technique on a rail-to-rail differential pair thus elevating the overall performance of the amplifier in terms of different performance parameters such as effective transconductance, output resistance, DC gain and unity gain frequency among others. One major advantage of the new proposed amplifier is its capability of providing a rail-to-rail stable operation without the need for compensation. The performance of the new proposed amplifier is tested on LTspice using 90nm CMOS technology under 1 Volts supply voltage and compared to other existing single stage amplifiers. Simulation results shows that the proposed amplifier provides a high DC gain, high effective transconductance and high output resistance while maintaining a stable operation with a phase margin of 80°. Obtained results also confirms that the amplifier exhibits rail-to-rail operation while maintaining a very low Total Harmonic Distortion (THD). The pulse response of the proposed amplifier indicates a fast response with a rise time and fall times almost twice as fast as the other examined topologies. Against Process, Voltage and Temperature (PVT) variations, the amplifier exhibits a robust performance as the DC gain variation range was within 20% only which is much less than the other examined topologies.

Dual Push–Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays

This brief presents the experimental validation of a low-power, large output swing, class-AB buffer amplifier for column drivers of active-matrix flat-panel displays. By exploiting two complementary input amplifiers and a dual-path push–pull output stage, the proposed circuit achieves high-drive performance and rail-to-rail operation. In addition, two current boosters allow area optimization of the output diving transistors by dynamically lowering their threshold voltage. Implemented in a standard triple-well CMOS 0.35- ${\mu }{\text{m}}$ technology and supplied from a 3-V supply, the proposed buffer amplifier can drive a 1-nF column line load within a 1.11- ${\mu }\text{s}$ settling time under a full voltage swing, while drawing only 1.6 ${\mu }\text{A}$ quiescent current and occupying 5562 ${\mu }{\text{m}}^{{2}}$ of silicon area. As compared to the state of the art, the best figure of merit (pF/ ${\mu }\text{s}{\cdot } {\mu }\text{A}$ ) is found.

Area-Efficient Time-Shared Digital-to-Analog Converter With Dual Sampling for AMOLED Column Driver IC’s

This paper presents a 24-channel time-shared 8-bit digital-to-analog converter (DAC) with dual sampling to minimize the effective channel area of the column driver integrated circuit (IC) for high-resolution active-matrix organic light emitting diodes (AMOLED). The proposed time-shared DAC significantly reduces the effective channel area of the column driver IC, since a single high-speed DAC is shared among multi channels. The dual-sampling architecture for the output amplifiers also reduces the power consumption of the column driver IC, where the operating time of the time-shared DAC and the output amplifier is efficiently handled during the limited 1-horizontal time. The sampling accuracy of the dual-sampling architecture is improved by a simple dummy switch and a source follower. The proposed time-shared DAC with the dual sampling is implemented by a 0.13- $\mu \text{m}$ high-voltage complementary metal-oxide-semiconductor process and integrated in a 960-channel column driver IC, while the effective channel area of the column driver IC is 5520 $\mu \text{m}^{2}$ . As a result of driving an 11-inch-wide quad extended graphics array AMOLED panel by using the prototype column driver IC, the panel uniformly generates a clear image.

42‐3: Invited Paper: A 4Gbps/lane Column Driver for 8K UHD 120Hz Display Larger than 85‐inches

A 4Gbps/lane column driver is implemented in 1.8V 0.13‐μm high‐voltage CMOS process for 8K UHD 120Hz displays. The proposed column driver presents auto‐calibrated 4Gbps receiver per lane to cover up to 8K UHD 120Hz 10bit display with two lanes and can drive 8K UHD panel larger than 85‐inches. Measured results show that a 4Gbps/lane column driver with auto equalizer calibration technique to adaptively compensate wide variation of channel length, power supply and temperature simultaneously.

42‐4: A Novel De‐Mux and 120Hz Driving Technology for High Resolution OLED Displays

We propose a novel in‐panel, TFT based de‐multiplex circuit for reducing column driver outputs. Each column driver output produces a command voltage for two neighboring column lines that are time multiplexed. De‐multiplexing is done on the array glass using TFT transistors. This approach supports higher‐frequency refresh rates for high‐resolution mobile OLED displays while minimizing display driver costs.

Touch Sensor Array With Integrated Drivers and Comparator Using a-IGZO TFTs

Integration of an amorphous indium–gallium–zinc–oxide thin-film transistor (TFT)-based self-capacitive touch sensor array with its peripheral drivers and readout circuits is reported. Each pixel consists of one touch electrode and five TFTs that enable a pixel-by-pixel driving scheme via integrated row and column drivers made of shift registers. Outputs from all sensor pixels are fed into an integrated comparator and compared with a reference voltage to generate a more readable low or high output level. A ~7 V difference between the touch and untouched states could be detected, making the proposed touch sensor a promising candidate for flexible electronics.

Design and Characterization of Active Matrix LED Microdisplays With Embedded Visible Light Communication Transmitter

This paper presents the design and characterization of the first active matrix light-emitting diode (AMLED) microdisplay with an embedded visible light communication (VLC) transmitter, enabling LED digital signage for location-based applications such as information broadcasters and indoor positioning beacons. The driver system-on-a-chip (SoC) integrates four identical macro-cells, each containing a pixel driver array, a row driver, a column driver, and a first-in first-out memory, to drive a wide quarter-VGA (WQVGA) display featuring 400 × 240 blue micro-LED (µLED) pixels fabricated on a single gallium nitride (GaN) substrate. The size of each µLED pixel is 30 × 30 µm2. At the system level, pulse-width modulation (PWM) superimposed with on–off keying modulation is proposed to accomplish grayscale control for display and simultaneously transmit VLC signal by modulating the µLED array. At the circuit level, a pixel driver cell composed of three transistors and one capacitor (3T1C) with a novel VLC function is employed to implement the control scheme. Flip-Chip bonding is adopted to establish connections between the WQVGA microdisplay and the AMLED driver SoC. Implemented in a 0.5-µm 2P3M CMOS process, the driver SoC enables a high-resolution microdisplay module to achieve 4-bit grayscale at a 100-Hz frame rate, while supporting 1.25-Mb/s VLC for a bit error rate 500 cm.

A 13‐bit universal column driver for various displays of OLED and LCD

AbstractA universal column driver is implemented in a 0.13‐µm high‐voltage CMOS process for not only TFT‐LCD but also OLED applications. The proposed column driver employs 13‐bit linear DAC to cover all gamma curves of display applications and address‐based configuration for intra‐ panel interface protocol to support both TV and IT applications. Measured results demonstrate the average voltage of output channels (AVO) is under 1mv, which satisfies 1‐LSB resolution at 18.5V of AVDD.

12-2:Distinguished Paper: A 13-bit Universal Column Driver for Various Displays of OLED and LCD

A universal column driver is implemented in a 0.13-µm highvoltage CMOS process for not only TFT-LCD but also OLED applications. The proposed column driver employs 13-bit linear DAC to cover all gamma curves of display applications and address-based configuration for intra- panel interface protocol to support both TV and IT applications. Measured results demonstrate the average voltage of output channels (AVO) is under 1mv, which satisfies 1-LSB resolution at 18.5V of AVDD.