Codec Engine Research Articles

Image Processing Using Discrete Wavelet Transform Based on OMAP3530

The discrete wavelet transform is usually realized by FPGA or DSP. This paper presents fast and valid image processing using discrete wavelet transform based on OMAP3530 chip which developed by TI(Texas Instruments). We employ the ARM+DSP dual-core OMAP3530 processor as the kernel of image processing. Linux Embedded System runs in the ARM side, DSP/BIOS System service run in the DSP side correspondingly. And the software development environment totally built upon the DVSDK (Digital Video Software Development Kit) which is provided by TI official website. Discrete wavelet transform algorithm adopted CE (Codec Engine) tools, which are the core of DVSDK. Finally, the image processing algorithm is inserted into CE. When the application program is running on the ARM side, the specific image is being conducted by CE on the DSP side.

3G intelligent video analysis system of vehicle on DM6446

Traditional vehicle video monitoring system enjoys not only large data but also dispersion, so it is difficult to retrieve and network. Wireless intelligent video analysis system of vehicle on DM6446 is designed to solve the problem. In which ARM side of DM6446 completes the main control of the system, then it calls intelligent video analysis algorithm in DSP side of DM6446 through the Codec Engine, which greatly improves the efficiency of the system, and the TCP/IP protocol controls data transmission in the WCDMA network. The monitoring display terminal gets video information by accessing the corresponding IP address. The experiment shows that the system designed realizes intelligent recognition of license plate and vehicle body color safely and reliably, and the wireless network is coherent. DOI: http://dx.doi.org/10.11591/telkomnika.v11i5.2477

The Design of 3G Wireless Network Video Acquisition System Based on the DM6446

The 3G wireless network video acquisition system based on the DM6446 is designed, which ARM side of DM6446 complete the main control functions of the system, then it calls H.264 video compression algorithm in DSP side of DM6446 through the Codec Engine, which greatly improves the efficiency of the system, and the RTP protocol control data transmission in the CDMA2000 network. The monitoring display terminal gets video resource by accessing the corresponding IP address. The experimental results show that the system designed completes wireless network video acquisition task safety and reliably, and the image is clear, also the video is coherent.

Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System

In a typical portable multimedia system, external access, which is usually dominated by block-based video content, induces more than half of total system power. Embedded compression (EC) effectively reduces external access caused by video content by reducing the data size. In this paper, an algorithm and a hardware architecture of a new type EC codec engine with multiple modes are presented. Lossless mode, and lossy modes with rate control modes and quality control modes are all supported by single algorithm. The proposed four-tree pipelining scheme can reduce 83% latency and 67% buffer size between transform and entropy coding. The proposed EC codec engine can save 62%, 66%, and 77% external access at lossless mode, half-size mode, and quarter-size mode and can be used in various system power conditions. With TSMC 0.18 mum 1P6M CMOS logic process, the proposed EC codec engine can encode or decode CIF 30 frame per second video data and achieve power saving of more than 109 mW. The EC codec engine itself consumes only 2 mW power.