Code Optimization Techniques Research Articles

Secure and Efficient NVM Usage for Embedded Systems Using AES-128 and Huffman Compression

Embedded systems are customized systems designed to meet functionality and specific usage purposes. These systems often grapple with challenges such as power interruptions, limited memory space, and the expectation of a long operational lifespan. It is in this context that Non-Volatile Memory (NVM) plays a vital role. NVM is a type of memory that ensures data persistence even in situations of temporary power loss or signal interruptions. Efficiently utilizing NVM is a critical necessity for the effectiveness and reliability of these systems. Efficient utilization of NVM necessitates the effective management of write and read cycles. Previous studies have demonstrated the efficient utilization of NVM sectors by ensuring that no garbage bytes remain unallocated. Previous studies have demonstrated the efficient utilization of NVM by compressing the data to be written into NVM using the Huffman compression algorithm, and filling sectors without any residual garbage bytes. This paper aspires to advance beyond prior research by integrating the Advanced Encryption Standard (AES-128) block encryption algorithm, aiming to optimize the utilization of NVM to a greater extent. The AES-128 algorithm provides data security with encryption and decryption operations. By applying AES-128 encryption to the data before writing it to the NVM, this work adds a data security layer to the developed software module. Data is divided into blocks using this algorithm. Each block is encrypted independently and then reassembled. The encryption process includes key management, substitution-permutation network layers, and multiple rounds, all of which make substantial contributions to high-level data security. The resulting encrypted data is compressed using the Huffman compression algorithm. This process enhances both the security and efficiency of data storage. The data is written to NVM with maximum efficiency, ensuring that no residual garbage bytes remain, upon the completion of the encryption and compression processes. This study surpasses previous research by enhancing storage security and efficiency through these processes. Moreover, the developed secure and efficient NVM usage, as it fills the NVM with data without leaving any garbage bytes, results in slower processing speed compared to standard NVM usage. Therefore, in future research, interventions with code optimization techniques can be applied to the developed algorithms to enhance write and read speeds.

An Inclusive Report on Robust Malware Detection and Analysis for Cross-Version Binary Code Optimizations

Numerous practices exist for binary code similarity detection (BCSD), such as Control Flow Graph, Semantics Scrutiny, Code Obfuscation, Malware Detection and Analysis, vulnerability search, etc. On the basis of professional knowledge, existing solutions often compare particular syntactic aspects retrieved from binary code. They either have substantial performance overheads or have inaccurate detection. Furthermore, there aren't many tools available for comparing cross-version binaries, which may differ not only in programming with proper syntax but also marginally in semantics. This Binary code similarity detection is existing for past 10 years, but this research area is not yet systematically analysed. The paper presents a comprehensive analysis on existing Cross-version Binary Code Optimization techniques on four characteristics: 1. Structural analysis, 2. Semantic Analysis, 3. Syntactic Analysis, 4. Validation Metrics. It helps the researchers to best select the suitable tool for their necessary implementation on binary code analysis. Furthermore, this paper presents scope of the area along with future directions of the research.

The principles of building a machine-learning-based service for converting sequential code into parallel code

This article presents a novel approach for automating the parallelization of programming code using machine learning. The approach centers on a two-phase algorithm, incorporating a training phase and a transformation phase. In the training phase, a neural network is trained using data in the form of Abstract Syntax Trees, with Word2Vec being employed as the primary model for converting the syntax tree into numerical arrays. The choice of Word2Vec is attributed to its efficacy in encoding words with less reliance on context, compared to other natural language processing models such as GloVe and FastText. During the transformation phase, the trained model is applied to new sequential code, transforming it into parallel programming code. The article discusses in detail the mechanisms behind the algorithm, the rationale for the selection of Word2Vec, and the subsequent processing of code data. This methodology introduces an intelligent, automated system capable of understanding and optimizing the syntactic and semantic structures of code for parallel computing environments. The article is relevant for researchers and practitioners seeking to enhance code optimization techniques through the integration of machine learning models.

Tuning three-dimensional tumor progression simulations on a cluster of GPGPUs

In the paper, we present the three-dimensional parallel simulator of tumor progression implemented for GPGPUs, together with an automatic model parameters tuning performed by evolutionary computations. We model the tumor growth by a set of Partial Differential Equations, describing the tumor density, tumor angiogenic factor, and damaged extra-cellular matrix, oxygen concentration, and a couple of auxiliary parameters, tumor pressure, tumor flux, and tumor cell sinks and sources. We also model the changes in the vasculature by the stochastic graph grammar model, expressing the angiogenesis process. We use the finite element method in the isogeometric analysis (IGA) context employing higher-order and continuity B-spline basis functions for approximation of the scalar fields modeling the tumor progression process. We show that replacing the traditional solver algorithm using the loop through elements into the alternative approach employing the loop through global basis functions enables for efficient parallelization on GPGPU. We also employ classical code optimization techniques, includes multithreading organization, memory access, and nesting and unrolling the loops. The experiments performed on the Prometheus supercomputer reported the speed-up of more than 171 times in comparison to analogous CPU simulator for the 2563 problem size. We also employ the GPGPU code for the solution of an inverse problem of identification of model parameters for patient-specific data. To achieve this goal, we synchronize three different GPGPUs simulators. We use evolutionary algorithms to find a proper model and synchronization parameters matching the prescribed medical data.

Near-Zero Downtime Recovery From Transient-Error-Induced Crashes

Due to the system scaling, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">transient errors</i> caused by external noise, e.g., heat fluxes and particle strikes, have become a growing concern for the current and upcoming exa-scale high-performance-computing (HPC) systems. Applications running on these systems are expected to experience transient errors more frequently than ever before, which will either lead them to generate incorrect outputs or cause them to crash. However, since such errors are still quite rare as compared to no-fault cases, desirable solutions call for low/no-overhead systems that do not compromise the performance under no-fault conditions and also allow very fast fault recovery to minimize downtime. In this article, we present <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IterPro</b> , a light-weight compiler-assisted resilience technique to quickly and accurately recover processes from transient-error-induced crashes. During the compilation of applications, <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IterPro</b> constructs a set of recovery kernels for crash-prone instructions. These recovery kernels are executed to repair the corrupted process states on-the-fly upon occurrences of errors, enabling applications to continue their executions instead of being terminated. When constructing recovery kernels, <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IterPro</b> exploits side effects introduced by induction variable based code optimization techniques based on loop unrolling and strength reduction to improve its recovery capability. To this end, two new code transformation passes are introduced to expose the side effects for resilience purposes. We evaluated <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IterPro</b> with 4 scientific workloads as well as the NPB benchmarks suite. During their normal execution, <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IterPro</b> incurs almost <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">zero</b> runtime overhead and a small, fixed <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">27MB</b> memory overhead. Meanwhile, <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IterPro</b> can recover on an average 83.55 percent of crash-causing errors within dozens of milliseconds with negligible downtime. We also evaluated <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IterPro</b> with parallel jobs running on 3072 cores and showed that <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IterPro</b> can successfully mask the impact of crash-causing errors by providing almost uninterrupted execution. Finally, we present our preliminary evaluation result for BLAS, which shows that <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IterPro</b> is capable of recovering failures in libraries with a very high coverage rate of 83 percent and negligible overheads. With such an effective recovery mechanism, <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IterPro</b> could tremendously mitigate the overheads and resource requirements of the resilience subsystem in future exa-scale systems.

A cost‐effective LoRa‐based customized device for agriculture field monitoring and precision farming on IoT platform

SummaryLow‐power wide area networks (LPWAN) applications are emerging as a new paradigm, over Internet of Things (IoT) platform. LoRa (long range) is playing a key role in information exchange between motes. This paper illustrates a mathematical optimization technique of LoRa modulation, i.e., frequency shift chirp modulation. Mathematical optimization for low power and LoRa has been validated with customized hardware designed for agricultural application. The performance analysis with channel modulation is mentioned in the networks. LoRa link budget concerning various obstacles calculated and losses are noted during testing. In context to the agricultural application, customized motes have been deployed in an agricultural field for field monitoring. The mathematical model is validated using a hardware device. Further data collection and data analysis are mentioned. Code optimization techniques are implemented to improve the overall efficiency of the device. Localization of sensor nodes also discussed to cover all the area of coverage. A comparative analysis is a showcased between SNR (signal‐to‐noise ratio) and RSSI (received signal strength indicator).

Enhancing Optimization Skills in Embedded Stream: Integrated Learning

Abstract Embedded system is one of the major focus areas in Electronics and Communication Engineering supported by relevant courses and projects at multiple levels. Students are well exposed in the embedded system verticals with industry supported labs, courses as well as industry guided projects for designing real time embedded systems. As embedded systems became bigger, intelligent and complex, millions of lines of code are to be optimized to meet system deadlines, fit into the available memory, and meet power requirements to achieve the desired functionality. Developing such embedded system, to meet multiple design constraints is a considerable challenge. In order to meet this challenge code optimization techniques at multiple levels are introduced in curriculum focusing on machine dependent and independent optimizations. Architecture specific machine dependent optimization techniques are addressed at basic courses like 8051 Microcontrollers and ARM processors, while machine dependent and independent optimization techniques are addressed at advanced courses like Real Time Embedded System and Course Projects which provides integrated experience. The courses are co-designed and delivered by both industry experts and in-house faculty. This exposure enables our students to be prepared for industry requirements and challenges, and has resulted in increased placements in embedded industries.

Optimal C code Implementation of OWGWA-CSS Algorithm on TMS320C6713 DSK

This paper presents the C code optimization of Oppositional Whale Grey Wolf Algorithm with Control Search Space (OWGWA-CSS) used for denoising EEG signal for its real-time implementation on floating point DSP processor TMS320C6713. In general, developers tried to speed up the program all-time which leads to increase in the code size so as increase the complexity as well as difficult readability. To make the code efficient it is important to optimize the C code. For optimizing the C code first, the MATLAB code is converted to C and then implemented on DSP processor. Here, multiple C code optimization techniques for the efficient implementation of OWGWA-CSS algorithm on DSP processor TMS320C6713 is presented. The aim of optimizing C code is to reduce the computational burden and speed up the process. The work done here is a step to minimize Millions Instruction Per Second (MIPS) used to execute the c- code of OWGWA-CSS EEG noise cancellation algorithm. The C code optimization is done by using Code Composer Studio (Integrated Development environment for TMS320C67xx series). CCS is used for optimization, profiling, debugging and implementation. After applying various C code optimization techniques 25% reduction in MIPS has been obtained.

Data-flow analysis and optimization for data coherence in heterogeneous architectures

Although heterogeneous computing has enabled developers to achieve impressive program speed-ups, the cost of moving and keeping data coherent between host and device may easily eliminate any performance gains achieved by acceleration. To deal with this problem, this paper introduces DCA: a pair of two data-flow analyses that determine how variables are used by host/device at each program point. It also introduces DCO, a code optimization technique that uses DCA information to: (a) allocate OpenCL shared buffers between host and devices; and (b) insert appropriate OpenCL function calls into program points so as to minimize the number of data coherence operations. We have used the AClang compiler to measure the impact of DCA and DCO when generating code from Parboil, Polybench and Rodinia benchmarks for a set of discrete/integrated GPUs. The experimental results showed speed-ups of up to 5.25x (average of 1.39x) on an ARM Mali-T880 and up to 8.87x (average of 1.66x) on an NVIDIA GPU Pascal Titan X.

Optimized implementation of digital signal processing applications with gapless data acquisition

This paper presents novel models and design optimization methods for gapless deep waveform applications, where continuous streams of data must be processed reliably without dropping any samples. The approaches developed in this paper involve unified dataflow-based modeling of the interfaces and signal processing functionality of gapless deep waveform analysis. Bottleneck actors (computational modules) in the resulting dataflow model are then identified and tackled with approximate computing techniques. These techniques are developed and configured carefully so that large performance gains are achieved while keeping reductions in signal processing accuracy to a manageable level. Efficient actor- and graph-level code optimization techniques are also applied to further improve real-time performance. In addition to providing accurate, real-time processing on the experimental platform used in our experiments, the algorithm- and model-based formulation of the contributions in this part promotes their general utility in deep waveform analysis and their retargetability to other platforms.

Efficient Computation of Array Factor and Sidelobe Level of Linear Arrays [EM Programmer's Notebook

The implementation of code to efficiently compute the array factor and sidelobe level (SLL) of linear antenna arrays in MATLAB and GNU Octave is considered in this article. The use of a fast Fourier transform (FFT) to compute the array factor is shown to be more efficient than other approaches. The automatic determination of the sidelobe region as a necessary step to computing the SLL is addressed. A number of code-optimization techniques in MATLAB and Octave are evaluated, including vectorization, memory allocation, and the use of built-in functions. Finally, an efficient function that can be used for the computation of the array factor and SLL of linear arrays in MATLAB and Octave is presented.

Code Optimization Techniques to Reduce Energy Consumption of Multimedia Applications in Hybrid Memory

This paper proposes code optimization techniques to reduce energy consumption of complex multimedia applications in a hybrid memory system with volatile dynamic random access memory (DRAM) and non-volatile spin-transfer torque magnetoresistive RAM (STT-MRAM). The proposed approach analyzes read/write operations for variables in an application. Based on the profile, variables with a high read operation are allocated to STT-MRAM, and variables with a high write operation are allocated to DRAM to reduce energy consumption. In this paper, to optimize code for real-life complicated applications, we develop a profiler, a code modifier, and compiler/link scripts. The proposed techniques are applied to a Fast Forward Motion Picture Experts Group (FFmpeg) application. The experiment reduces energy consumption by up to 22%.

Non-Binary LDPC Codes for Magnetic Recording Channels: Error Floor Analysis and Optimized Code Design

In this paper, we provide a comprehensive analysis of the error floor along with code optimization guidelines for structured and regular non-binary low-density parity-check (NB-LDPC) codes in magnetic recording (MR) applications. While the topic of the error floor performance of binary LDPC codes over additive white Gaussian noise (AWGN) channels has recently received considerable attention, very little is known about the error floor performance of NB-LDPC codes over other types of channels, despite the early results demonstrating superior characteristics of NB-LDPC codes relative to their binary counterparts. We first show that, due to the outer looping between the detector and the decoder in the receiver, the error profile of NB-LDPC codes over partial-response (PR) channels is qualitatively different from the error profile over AWGN channels—this observation motivates us to introduce new combinatorial objects aimed at capturing decoding errors that dominate the PR channel error floor region. We call these objects balanced absorbing sets (BASs), which are viewed as a special subclass of previously introduced absorbing sets (ASs). Aided by these new objects (BASs), we develop a method that combines analytical equations and biased simulations to predict the error floor performance of NB-LDPC codes over PR channels without the need to execute extensive Monte Carlo (MC) simulations. We show that explicitly incorporating the inter-symbol interference of MR channels into our prediction method makes the accuracy of the error floor estimate within 0.2 of an order of magnitude from the traditional MC simulation. In addition, we prove that, due to the more restrictive definition of BASs (relative to the more general class of ASs), an additional degree of freedom can be exploited in the code design for PR channels. We then demonstrate that the proposed code optimization aimed at removing dominant BASs offers performance improvements in the frame error rate in the error floor region by up to 2.5 orders of magnitude over the unoptimized designs. Our code optimization technique carefully, yet provably, removes BASs from the code while preserving its overall structure (node degree, quasi-cyclic property, regularity, and so forth). The resulting codes outperform the existing binary and NB-LDPC solutions for PR channels by about 2.5 and 1.25 orders of magnitude, respectively.

Automatically scheduling halide image processing pipelines

The Halide image processing language has proven to be an effective system for authoring high-performance image processing code. Halide programmers need only provide a high-level strategy for mapping an image processing pipeline to a parallel machine (a schedule ), and the Halide compiler carries out the mechanical task of generating platform-specific code that implements the schedule. Unfortunately, designing high-performance schedules for complex image processing pipelines requires substantial knowledge of modern hardware architecture and code-optimization techniques. In this paper we provide an algorithm for automatically generating high-performance schedules for Halide programs. Our solution extends the function bounds analysis already present in the Halide compiler to automatically perform locality and parallelism-enhancing global program transformations typical of those employed by expert Halide developers. The algorithm does not require costly (and often impractical) auto-tuning, and, in seconds, generates schedules for a broad set of image processing benchmarks that are performance-competitive with, and often better than, schedules manually authored by expert Halide developers on server and mobile CPUs, as well as GPUs.

Alternatives of profile-guided code optimizations for one-stage compilation

Optimizing compilers increase the resulting code performance by carrying out a number of code optimization techniques. Profile information assistance for code optimizations gives an opportunity to greatly increase the code performance in some cases. However, the impossibility to provide a representative training execution often leads to the decline in efficiency of profile-dependent code optimizations. This paper investigates the main causes of the performance loss for the one-stage optimization as compared to the profileguided optimization (PGO) and introduces some alternative compilation techniques to reduce this loss. The effectiveness of these techniques is evaluated for a VLIW-architecture Elbrus compiler.

LDPC code optimization techniques to improve the error correction threshold

Non-empty stopping sets, which are the main reason for achieving a threshold of errors in data transmission channels, are studied. New algorithm of transfer smallest stopping sets and stop distance of any LDPC code is proposed. More functional and flexible technique of splitting-and-filling is proposed. Time for which will be transferred the smallest stopping sets and founded stop distance of any LDPC code is calculated

Smart Coding using New Code Optimization Techniques in Java to Reduce Runtime Overhead of Java Compiler

Java is a popular object oriented programming language suitable for writing Java programs. Sometimes programmers spend most of the time to increase the execution time of the program, but simultaneously its effect on code size. Therefor the code become more complex and unreliable, so this leads to reduce the efficiency of code. Today so many compilers are exist like c, javac,c++,cobol,etc.we studied the code optimization techniques for java compiler separately and that time we come across some new code optimization strategies which is the smart way to do the coding in java. In this paper we applied some new java code optimization techniques on existing code. We verify the code optimization, performance using our executor. These code optimization strategies indirectly help to reduce the work of garbage collection, data structure and also work on loop optimization. So the results which we found after doing experimentations are quite satisfactory as compare to original results. so these techniques are help to improve the code quality.

Tokamak equilibrium reconstruction code LIUQE and its real time implementation

Equilibrium reconstruction consists in identifying, from experimental measurements, a distribution of the plasma current density that satisfies the pressure balance constraint. The LIUQE code adopts a computationally efficient method to solve this problem, based on an iterative solution of the Poisson equation coupled with a linear parametrisation of the plasma current density. This algorithm is unstable against vertical gross motion of the plasma column for elongated shapes and its application to highly shaped plasmas on TCV requires a particular treatment of this instability. TCV's continuous vacuum vessel has a low resistance designed to enhance passive stabilisation of the vertical position. The eddy currents in the vacuum vessel have a sizeable influence on the equilibrium reconstruction and must be taken into account. A real time version of LIUQE has been implemented on TCV's distributed digital control system with a cycle time shorter than 200μs for a full spatial grid of 28 by 65, using all 133 experimental measurements and including the flux surface average of quantities necessary for the real time solution of 1.5 D transport equations. This performance was achieved through a thoughtful choice of numerical methods and code optimisation techniques at every step of the algorithm, and was coded in Matlab and Simulink for the off-line and real time version respectively.

Low-Power High-Efficiency Video Decoding using General-Purpose Processors

In this article, we investigate how code optimization techniques and low-power states of general-purpose processors improve the power efficiency of HEVC decoding. The power and performance efficiency of the use of SIMD instructions, multicore architectures, and low-power active and idle states are analyzed in detail for offline video decoding. In addition, the power efficiency of techniques such as “race to idle” and “exploiting slack” with DVFS are evaluated for real-time video decoding. Results show that “exploiting slack” is more power efficient than “race to idle” for all evaluated platforms representing smartphone, tablet, laptop, and desktop computing systems.

Efficient code generation in a region-based dynamic binary translator

Region-based JIT compilation operates on translation units comprising multiple basic blocks and, possibly cyclic or conditional, control flow between these. It promises to reconcile aggressive code optimisation and low compilation latency in performance-critical dynamic binary translators. Whilst various region selection schemes and isolated code optimisation techniques have been investigated it remains unclear how to best exploit such regions for efficient code generation. Complex interactions with indirect branch tables and translation caches can have adverse effects on performance if not considered carefully. In this paper we present a complete code generation strategy for a region-based dynamic binary translator, which exploits branch type and control flow profiling information to improve code quality for the common case. We demonstrate that using our code generation strategy a competitive region-based dynamic compiler can be built on top of the LLVM JIT compilation framework. For the ARM-V5T target ISA and SPEC CPU 2006 benchmarks we achieve execution rates of, on average, 867 MIPS and up to 1323 MIPS on a standard X86 host machine, outperforming state-of-the-art QEMU-ARM by delivering a speedup of 264%.