Code Compression Techniques Research Articles

SPGMVC: Multiview Clustering via Partitioning the Signed Prototype Graph.

Multiview clustering (MVC) has been widely studied in machine learning and data mining for its capability of improving clustering performance by fusing the information from multiview data. In the past decade, a large number of MVC methods have made impressive progress, but most of them suffer from computational burdens, especially in large-scale tasks. Binary MVC (BMVC) is proposed to address this issue by representing the large-scale high-dimensional dataset as a group of consensus and low-dimensional binary codes. However, current BMVC-based approaches generate the clustering by executing binary k -means on the obtained binary codes, which fail to capture the embedded geometric information, leading to poor clustering performance. In addition, parameter selection is another "mission impossible" in unsupervised learning tasks including MVC. To tackle these challenges, a framework of multiview clustering via partitioning the signed prototype graph (SPGMVC) is proposed in this work. The SPGMVC framework offers several contributions. First, SPGMVC is designed as a unified framework for MVC. It combines effective technologies, such as consensus binary coding, code compression (CC), signed prototype graph (SPG) partitioning, and prototype-based cluster assignment. Second, SPGMVC partitions the signed graph (SG) based on the relationships between positive and negative edges. By capturing the underlying structure of the data, this partitioning strategy improves clustering accuracy (ACC). CC techniques are applied to reduce the graph's scale, enabling further partitioning and enhancing computational efficiency. Third, SPGMVC employs an alternate minimizing strategy to efficiently handle the optimization problem. This strategy has nearly linear time and space complexity with respect to the data volume, making it suitable for large-scale tasks. Fourth, SPGMVC proposes an automatic parameter selection strategy, eliminating the need for extensive parameter exploration. Comprehensive experiments illustrate the superiority of our model. The implementation of SPGMVC is available at: https://github.com/gepingyang/PSGMVC.

Dynamic code compression for JavaScript engine

AbstractWeb applications created using web languages such as HTML, CSS, and JavaScript are widely used regardless of execution environments, owing to their portability and popularity. Since JavaScript language is conventionally used for complex computations in large‐scale web apps, many optimization techniques have been proposed to accelerate the JavaScript performance. However, most of these optimizations speed up JavaScript engines at the expense of consuming more memory. Hence, memory consumption becomes an additional concern in the JavaScript field. Based on the research on memory status, we unearthed that a substantial portion of the heap memory is allocated for JavaScript source code, particularly in lightweight JavaScript engines, which may range from 13.2% to a maximal 52.5% of the entire heap. To resolve this memory issue, this article suggests a new memory optimization method, called dynamic code compression that dynamically compresses the source code and keeps its compressed form instead of the source string. A novel heuristic is proposed to timely compress the source code. We also re‐design the internal structure of the JavaScript engine to efficiently compress the source code without incurring any conflict. Using our code compression method, we could reduce the entire heap memory by up to 43.3% and consistently downsize the overall heap size. From an evaluation of standard benchmarks, our approach showed just 2.7% degradation in performance with negligible compression overhead, proving the feasibility of the code compression technique.

Statistics-Based Chain Code Compression with Decreased Sensitivity to Shape Artefacts

Chain codes compactly represent raster curves, but there is still a lot of room for improvement by means of data compression. Several statistics-based chain code compression techniques assign shorter extra codes to frequent pairs of consecutive symbols. Here we systematically extend this concept to patterns of up to six symbols. A curve may be represented by any of the exponentially many overlapped chains of codes, and the dynamic programming approach is proposed to determine the optimal chain. We also propose utilization of multiple averaged hard coded pseudo-statistical models, since the exact statistical models of individual curves are often huge, and they can also significantly differ from each other. A competitive compression efficiency is assured in this manner and, as a pleasant side effect, this efficiency is less affected by the curve’s shape, rasterization algorithm, noise, and image resolution, than in other contemporary methods, which surprisingly do not pay any attention to this problem at all.

Recent developments in code compression techniques for embedded systems

Embedded applications software code is increasingly growing in size. Whereas the entire code of all control panels in a car provided for roughly a few 100 K code lines a decade ago, a single control panel such as the engine control can now have up to 1million code lines. With these help of good approach, common scenarios are developed for other, even for mobiles, embedded systems like PDA’s, cell phones etc. However, increasing software size requires greater memory and can therefore raise the cost of an embedded system considerably. The starting of this pattern was already established in the early 1990 s. The compressed code is created by compressing the binary numbers using a code compression tool (at the time of design) is stored in the instruction memory of the embedded devices. The compressed instructions are decompressed and implemented by the processor at the time of startup. One of the serious challenges is that the tables will become wide in size and therefore decrease the benefits of compressing the code that could be accessed. Although the whole research in this area has mostly concentrated on improving greater code compression without specifically targeting the issue of wide look-up table sizes.

CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems

Code compression is widely used to reduce the footprint of code memory in cost-sensitive embedded systems. However, despite the small code size, the decompressor and the address translator required to support the code compression incur energy and area overheads. To reduce such overheads while still supporting code compression, we co-architect the instruction cache and decompression system (CID). In CID, each component is placed at the optimal location and the instruction cache is redesigned to recognize the compression state and retain the original address, through the cache division and address space decompression process. As a result of the cache division, the energy consumption and area overheads of the CID instruction cache are reduced. Since the decompressor overhead depends on the code compression technique, we propose a new code compression technique called entropy-based pattern code compression, which reduces overheads of the decompressor. Our experimental results show that the total energy consumption of the instruction cache and decompression system is reduced by up to 29.7 percent and their area is reduced by up to 15.4 percent compared to the post-cache architecture with almost no performance degradation, while achieving an 18.8 percent improvement in the compression ratio compared to the state-of-the-art code compression technique.

An Improved Code Compression Technique for Embedded Systems Using Optimal Separated Dictionaries

An Improved Code Compression Technique for Embedded Systems Using Optimal Separated Dictionaries

High performance decoding aware FPGA bit-stream compression using RG codes

FPGA design for complex applications need high capacity of configuration memory. To fullfil the large memory requirement, higher end FPGAs are required and it leads to higher cost. In order to reduce the cost constraint, bit-stream compression is prominently involved to reduce the bit-stream size and the memory requirement of FPGA configuration. In this paper new code compression techniques are proposed with minimum cost. The proposed code compression techniques RG-1 and RG-2 codes are designed based on the combination of run length and Golomb coding. The proposed RG codes overcome the limitation of both run length and Golomb coding techniques. The main contribution of this work is to analyze the proposed work in terms of number of 1’s, number of transitions and size of compressed bits. The comparison result shows that the RG code is more robust when compared to other traditional code compression techniques. The results shows that CR improvement of 9 and 5% compare with RLE for the RG-1 and RG-2 respectively and CR improvement of 7 and 2% compare with golomb for the RG-1 and RG-2 respectively.

An efficient code compression for MIPS32 processor using dictionary and bit-mask based static and dynamic frequency algorithm

Purpose Memory plays a vital role in designing embedded systems. A larger memory can accommodate more and larger applications but increases cost area, as well as energy requirements. Hence, the purpose of this paper is to propose code compression techniques to solve this issue by minimizing the code size of the application program by compressing the instructions with higher static frequency. Design/methodology/approach The idea is based on the static and dynamic frequency-based algorithm combined with bit mask and dictionary-based algorithm for MIPS32 processor, in order to minimize the code size and improves compression ratio. Findings The experimental result shows that the proposed system achieves up to 67 percent compression efficiency. Originality/value The paper presents enhanced versions of the code compression technique.

Design and evaluation of compact ISA extensions

The modern embedded market massively relies on RISC processors. The code density of such processors directly affects memory usage, an expensive resource. Solutions to mitigate this issue include code compression techniques and ISAs extensions with reduced instructions bit-width, such as Thumb2 and MicroMIPS. This paper proposes a 16-bit extension to the SPARC processor, the SPARC16. Additionally, we provide the first methodology for generating 16-bit ISAs and evaluate compression among different 16-bit extensions. SPARC16 programs can achieve better compression ratios than other extensions, attaining results as low as 67%. Moreover, SPARC16 reduces cache miss rates up to 9%, requiring smaller caches than SPARC processors to achieve the same performance; a cache size reduction that can reach a factor of 16.

Studying the code compression design space – A synthesis approach

Embedded domain has witnessed the application of different code compression methodologies on different architectures to bridge the gap between ever-increasing application size and scarce memory resources. Selection of a code compression technique for a target architecture requires a detailed study and analysis of the code compression design space. There are multiple design parameters affecting the space, time, cost and power dimensions. Standard approaches of exploring the code compression design space are tedious, time consuming, and almost impractical with the increasing number of proposed compression algorithms. This is one of the biggest challenges faced by an architect trying to adopt a code compression methodology for a target architecture. We propose a novel synthesis based tool-chain for fast and effective exploration of the code compression design space and for evaluation of the tradeoffs. The tool-chain consists of a frontend framework that works with different compression/decompression schemes and a backend with high-level-synthesis, logic-synthesis, and power estimation tools to output the critical design parameters. We use the tool-chain to effectively analyze different code compression/decompression schemes of varying complexities.

VLSI IMPLEMENTATION OF EFFICIENT CODE COMPRESSOR FOR BIO-SIGNAL PROCESSORS

This paper describes a highly integrated VLSI implementation of code compression technique that can be used for Bio signal processors with reduced storage. An increasing concern in processor design is improved Code density, since it reduces the need for the scarce resource memory and also implicitly improves processor performance in terms of further important design Parameters like power consumption and performance. Code compression also improves the portability that enables System on Chip (SOC) implementation. A dictionary based data compression technique which provides a substantial improvement in the compression efficiency without introducing any additional decompression penalty is introduced here for compressing of neural signals like Electroencephalogram (EEG), Electrocardiogram (ECG), and Electromyogram (EMG). This technique shows 28% of memory saving when implemented in VLSI technology. This may also reduce the power Consumption, since memory consumes a significant amount of processor's power.

Huffman-based code compression techniques for embedded processors

The size of embedded software is increasing at a rapid pace. It is often challenging and time consuming to fit an amount of required software functionality within a given hardware resource budget. Code compression is a means to alleviate the problem by providing substantial savings in terms of code size. In this article we introduce a novel and efficient hardware-supported compression technique that is based on Huffman Coding. Our technique reduces the size of the generated decoding table, which takes a large portion of the memory. It combines our previous techniques, Instruction Splitting Technique and Instruction Re-encoding Technique into new one called Combined Compression Technique to improve the final compression ratio by taking advantage of both previous techniques. The instruction Splitting Technique is instruction set architecture (ISA)-independent. It splits the instructions into portions of varying size (called patterns) before Huffman coding is applied. This technique improves the final compression ratio by more than 20% compared to other known schemes based on Huffman Coding. The average compression ratios achieved using this technique are 48% and 50% for ARM and MIPS, respectively. The Instruction Re-encoding Technique is ISA-dependent. It investigates the benefits of reencoding unused bits (we call them reencodable bits) in the instruction format for a specific application to improve the compression ratio. Reencoding those bits can reduce the size of decoding tables by up to 40%. Using this technique, we improve the final compression ratios in comparison to the first technique to 46% and 45% for ARM and MIPS, respectively (including all overhead that incurs). The Combined Compression Technique improves the compression ratio to 45% and 42% for ARM and MIPS, respectively. In our compression technique, we have conducted evaluations using a representative set of applications and we have applied each technique to two major embedded processor architectures, namely ARM and MIPS.

Squashing code size in microcoded IPs while delivering high decompression speed

Microcoded customized IPs offer superior performance and direct programmability of micro-architectural structures compared to instruction-based processors, yet at the cost of drastically enlarged code sizes. Code compression can deliver size reductions but necessitates attention to performance issues, so that the performance benefits of microcoded IPs are not squandered in the process. To attain this goal, we propose in this paper a fast code compression technique through exploiting the fact that the microcodes contain a sizable amount of unspecified bits. Although the values and the positions of the specified bits are highly irregular, the proposed technique can still flexibly and precisely fill in these fully specified bits through utilizing a linear network. The linear property inherent in the compression strategy in turn enables the development of an extremely low-overhead decompression engine. At runtime, the decompressed code can be generated in such a way that all the specified bits can be filled as required by a fixed-bandwidth XOR network. The combination of the proposed flexible XOR-based network with a minimum two-level storage for highly specified fields, such as immediate values, offers utmost code compression, attained within a negligible amount of performance and hardware overhead.

Universal Decremental Redundancy Compression with Fountain Codes

A new universal noise-robust lossless compression algorithm based on a decremental redundancy approach with Fountain codes is proposed. The binary entropy code is harnessed to compress complex sources with the addition of a preprocessing system in this paper. Both the whole binary entropy range compression performance and the noise-robustness of an existing incremental redundancy Fountain code compression technique are exceeded. A new autocorrelation-based symbol length estimator, the Burrows-Wheeler block sorting transform (BWT) and Move-to-Front transformation (MTF) with a new entropy ordered MTF indices transformation reduces the binary entropy of a universal data source. The preprocessed input source is coded with a new modified incremental degree LT-code (Luby Transform) and a low-complexity decremental redundancy algorithm is used to compress the Fountain-coded source. The improved compression and robustness against transmission errors with our novel incremental degree puncturing decremental redundancy algorithm is shown. The universal (complex memory source) compression performance of the proposed system is shown to achieve appreciable compression.

Improved Dictionary-Based Code-Compression Schemes with XOR Reference for RISC/VLIW Architecture

Embedded systems are constrained by the available memory, and code-compression techniques address this issue by reducing the code size of application programs. The main challenge for the development of an effective code-compression technique is to reduce code size without affecting the overall system performance. Dictionary-based code-compression schemes are the most commonly used code-compression methods, because they can provide both good compression ratio and fast decompression. We propose an XOR-based reference scheme that can enhance the compression ratio on all the existing dictionary-based algorithms by changing the distribution of the symbols. Our approach works on all kinds of computer architecture with fixed length instructions, such as RISC or VLIW. Experiments show that our approach can further improve the compression ratio with nearly no hardware, performance, and power overheads.

Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs

Horizontal Microcoded Architecture (HMA) is a paradigm for designing programmable high-performance processing elements (PEs). However, it suffers from large code size, which can be addressed by compression. In this article, we study the code size of one of the new HMA-based technologies called No-Instruction-Set Computer (NISC). We show that NISC code size can be several times larger than a typical RISC processor, and we propose several low-overhead dictionary-based code compression techniques to reduce its code size. Our compression algorithm leverages the knowledge of “don't care” values in the control words and can reduce the code size by 3.3 times, on average. Despite such good results, as shown in this article, these compression techniques lead to poor FPGA implementations because they require many on-chip RAMs. To address this issue, we introduce an FPGA-aware dictionary-based technique that uses the dual-port feature of on-chip RAMs to reduce the number of utilized block RAMs by half. Additionally, we propose cascading two-levels of dictionaries for code size and block RAM reduction of large programs. For an MP3 application, a merged, cascaded, three-dictionary implementation reduces the number of utilized block RAMs by 4.3 times (76%) compared to a NISC without compression. This corresponds to 20% additional savings over the best single level dictionary-based compression.

Bitmask-Based Code Compression for Embedded Systems

Embedded systems are constrained by the available memory. Code-compression techniques address this issue by reducing the code size of application programs. It is a major challenge to develop an efficient code-compression technique that can generate substantial reduction in code size without affecting the overall system performance. We present a novel code-compression technique using bitmasks, which significantly improves the compression efficiency without introducing any decompression penalty. This paper makes three important contributions. 1) It develops an efficient bitmask-selection technique that can create a large set of matching patterns. 2) It develops an efficient dictionary-selection technique based on bitmasks. 3) It proposes a dictionary-based code-compression algorithm using the bitmask- and dictionary-selection techniques that can significantly reduce the memory requirement. To demonstrate the usefulness of our approach, we have performed code compression using applications from various domains and compiled for a wide variety of architectures. Our approach outperforms the existing dictionary-based techniques by an average of 20%, giving a compression ratio of 55%-65%.

Automated reduction of the memory footprint of the Linux kernel

The limited built-in configurability of Linux can lead to expensive code size overhead when it is used in the embedded market. To overcome this problem, we propose the application of link-time compaction and specialization techniques that exploit the a priori known, fixed runtime environment of many embedded systems. In experimental setups based on the ARM XScale and i386 platforms, the proposed techniques are able to reduce the kernel memory footprint with over 16%. We also show how relatively simple additions to existing binary rewriters can implement the proposed techniques for a complex, very unconventional program, such as the Linux kernel. We note that even after specialization, a lot of seemingly unnecessary code remains in the kernel and propose to reduce the footprint of this code by applying code-compression techniques. This technique, combined with the previous ones, reduces the memory footprint with over 23% for the i386 platform and 28% for the ARM platform. Finally, we pinpoint an important code size growth problem when compaction and compression techniques are combined on the ARM platform.

Code compression for embedded VLIW processors using variable-to-fixed coding

In embedded system design, memory is one of the most restricted resources, posing serious constraints on program size. Code compression has been used as a solution to reduce the code size for embedded systems. Lossless data compression techniques are used to compress instructions, which are then decompressed on-the-fly during execution. Previous work used fixed-to-variable coding algorithms that translate fixed-length bit sequences into variable-length bit sequences. In this paper, we present a class of code compression techniques called variable-to-fixed code compression (V2FCC), which uses variable-to-fixed coding schemes based on either Tunstall coding or arithmetic coding. Though the techniques are suitable for both reduced instruction set computer (RISC) and very long instruction word (VLIW) architectures, they favor VLIW architectures which require a high-bandwidth instruction prefetch mechanism to supply multiple operations per cycle, and fast decompression is critical to overcome the communication bottleneck between memory and CPU. Experimental results for a VLIW embedded processor TMS320C6x show that the compression ratios using memoryless V2FCC and Markov V2FCC are around 82.5% and 70%, respectively. Decompression unit designs for memoryless V2FCC and Markov V2FCC are implemented in TSMC 0.25-/spl mu/m technology.

Code compression by register operand dependency

This paper proposes a dictionary-based code compression technique that maps the source register operands to the nearest occurrence of a destination register in the predecessor instructions. The key idea is that most destination registers have a great possibility to be used as source registers in the following instructions. The dependent registers can be removed from the dictionary if this information can be specified otherwise. Such destination–source relationships are so common that making use of them can result in much better code compression. After removing the dependent register operands, the original dictionary size can be reduced significantly. As a result, the compression ratio can benefit from: (a) the reduction of dictionary size due to the removal of dependent registers, and (b) the reduction of program encoding due to the reduced number of dictionary entries. A set of programs has been compressed using this feature. The compression results show that the average compression ratio is reduced to 38.41% on average for MediaBench benchmarks compiled for MIPS R2000 processor, as opposed to 45% using operand factorization.