CMOS Voltage-controlled Oscillator Research Articles

CMOS Voltage-Controlled Oscillator with Complementary and Adaptive Overdrive Voltage Control Structures

This paper displays a voltage-controlled oscillator (VCO) with high performance implemented in 0.18 µm CMOS. The proposed CMOS VCO adopts a current-reused method, analog coarse and fine tuning mechanisms, and an adaptive overdrive voltage control structure to increase the overall performance, such as the power dissipation, phase noise, and tuning range, and has a robust start-up condition. The current-reused complementary structure with higher transistor transconductances is to save power consumption; the analog coarse and fine tuning mechanisms are to effectively widen the tuning range; and the adaptive overdrive voltage control technique is to change the transconductances of the transistors to improve power consumption by reasonably biasing the gate and body terminals in a class-AB mode to adjust the threshold voltage of the NMOS transistors. The proposed CMOS VCO adopts the class-AB mode to improve the overall performance and the start-up condition. The figure-of-merit (FOM) and FOM with tuning range (FOMT) are used in evaluating the CMOS VCO performance. The measured phase noise at 1 MHz and 10 MHz offsets is –130.34 dBc/Hz and –150.96 dBc/Hz at the 3.38 GHz operating frequency, respectively. The proposed CMOS VCO has a tuning range between 2.85 and 3.62 GHz corresponding to 23.8% for the fifth-generation (5G) wireless communication applications. The proposed CMOS VCO core using a 1.4-V supply consumes 7.5 mW DC power. The FOMs and FOMTs at 1- and 10-MHz offsets are −192.2, −192.8, −199.7, and −200.3 dBc/Hz, respectively, from the 3.38 GHz output frequency.

K-band CMOS voltage-controlled oscillator using tail current modulation with half-output frequency

A CMOS voltage-controlled oscillator (VCO) using half-oscillation frequency signals as switched biasing is proposed to simultaneously improve the phase noise and DC-to-RF conversion efficiency. The effect of the flicker noise caused by the tail current source, which is the dominant factor of the VCO phase noise, can be reduced by the modulation using the half-frequency signals of the output. The conversion efficiency of the proposed VCO is improved by the leakage of the second harmonics of the modulation signal at the drain node of the current source, which is the same as the oscillation frequency of the VCO, thereby increasing the output power. The differential half-frequency signals are generated in the frequency divider, designed with the current-mode logic for minimizing the effect of parasitic components at high-frequency operation, which constitutes the frequency synthesizer without any additional circuits. The proposed VCO with the divider was fabricated on the size of 0.4 × 0.61 mm2 using a 65-nm CMOS process, including all pads. The measurement results showed a tuning range of 11.2% at the K-band and a phase noise of –109.86 dBc/Hz at the 1-MHz offset. The peak output power and DC-to-RF efficiency were measured to be 0.95 dBm and 16.64%, respectively, at the supply voltage of 1.2 V. A figure of merit of the proposed VCO was calculated to be –188.03 dBc/Hz.

Design and Optimization of an Ultra-Low-Power Cross-Coupled LC VCO with a DFF Frequency Divider for 2.4 GHz RF Receivers Using 65 nm CMOS Technology

This article presents the design and optimization of a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider. The VCO is designed for the low-power and low-phase-noise applications of 2.4 GHz IoT/BLE receivers and wireless sensor devices. The proposed design comprises the proper stacking of an LC VCO and a DFF frequency divider and is simulated using a TSMC 65 nm CMOS technology, and it has a tuning range of 4.4 to 5.7 GHz. The voltage headroom is preserved using a high-impedance on-chip passive inductor at the tail for filtering and enabling true differential operation. The VCO and frequency divider consume as low as 2.02 mW altogether, with the VCO section consuming only 0.47 mW. The active area of the chip including the pads is only 0.47 mm2. The designed VCO achieved a much better phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with 1.2 V supply voltages. The design produced a much better FoM of −196.44 dBc/Hz compared to other related research.

Differential RVCO with low power, low phase noise and wider tuning range for PLL application

ABSTRACT A differential ring CMOS voltage-controlled oscillator (VCO) with dual-delay path topology is proposed in this paper. In this work, the focus area is to improve the tuning range of VCO and phase noise performance of the VCO. The dual-delay path topology is used with P-MOS as load in series with negative-skewed delay transistors. This design gives the wider tuning range and this increases the phase noise performance of the VCO. After the post-layout simulation, frequency tuning range and power dissipation range are 730 MHz to 2.81 GHz and from 1.32 mW to 4.62 mW respectively. The phase noise for this VCO is −97.35 dBc/Hz at 1 MHz offset. The technology used in this work was taken from the library of SCL 180 nm technology. This design exhibits excellent phase noise performance.

-Band Class-B VCO in 22 nm FD-SOI With Inductive Source Degeneration of the Tail Current Source

In this work, a voltage-controlled oscillator (VCO) in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band has been introduced that uses the proposed technique named “inductive source degeneration of the tail current source.” The contribution of this work is that the auxiliary resonator is placed differently than the conventional works so that it leads to a more compact solution without affecting the phase noise (PN). Based on the simulation results, for the same device sizes and power consumption, the proposed Class-B method reduces the PN by 1.5 dB than the conventional one at 1 MHz offset from 24 GHz center frequency. VCO has been fabricated on a die area of 0.026 mm2 in the 22 nm fully depleted silicon on insulator (FD-SOI) technology. The measurement was done in the free-running mode, and the results show a PN of −122.4 dBc/Hz at 10 MHz offset from the center frequency of 23.8 GHz. The power consumption of the VCO core is 14.4 mW with 1 V supply voltage. According to the measurement results, this work achieves <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\text {FoM}_{A}}$ </tex-math></inline-formula> , a figure of merit which considers the VCO core area, of −194.2 dBc/Hz at 10 MHz offset from the center frequency, featuring state-of-the-art among the CMOS VCOs in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band.

A 2-Bit Voltage-Controlled Oscillator (VCO) for Multiband Wireless Applications

This letter presents a fully-integrated 2-bit CMOS voltage-controlled oscillator (VCO) along with a 2-bit buffer, which delivers the highest RF output power among recently reported state-of-the-art to the best of the authors’ knowledge. The proposed 2-bit VCO is designed and fabricated in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18-\mu \text{m}$ </tex-math></inline-formula> CMOS process with a die size of 1.2 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$ </tex-math></inline-formula> 1.2 mm, which covers four frequency bands of interest. Fine-tuning at each of the four frequency bands is also obtained by utilizing two varactors. The proposed 2-bit VCO delivers a single-ended output power of 6.5/6.8/10.6/12.5 dBm at 0.930/1.157/1.436/1.917 GHz, respectively. This 2-bit VCO can cover frequency ranges of 930–1005, 1046–1157, 1248–1436, and 1540–1917 MHz, thus providing a total frequency bandwidth of 751 MHz. The proposed 2-bit VCO at each frequency band demonstrates −99, −93, −90, and −86 dBc/Hz for phase noise, and −150, −150, −160, and −168 dBc/Hz for figure-of-merit (FOM), respectively.

A 2.2-mW 23 GHz CMOS VCO using high-quality factor complementary split ring resonator with a −195dBc/Hz FOM

Novel resonators to enhance the performance of a Voltage-Controlled-Oscillator (VCO) utilizing single and double ring resonators to improve the loaded-quality (QL) factor of the resonator are introduced, and their effectiveness is demonstrated by designing low-phase-noise (PN) K-band VCO. Also, the size of the double-ring-resonator (DRR) is compacted by 40% and its QL-factor is increased. The resonators are designed using HFSS. First Complementary-Single-Split-Ring (CSSRR) is designed and optimized to maximize its QL-factor, then three resonators (meander-line-split-ring, double-ring, compacted-double-ring resonators) are studied to increase their QL-factor compared to the CSSRR. The QL-factor of the DRR is 30 ± 1 at 20–60 GHz with a size of 140 µm*90 µm while the compacted-double-ring-resonator (Compacted DRR) has a size of 120 µm*60 µm and its QL-factor is increased by 25% compared to vertical-DRR. The resulting QL-factor of the proposed resonator is improved significantly that, in return, enhances PN. The resonators are designed in 0.18 μm-CMOS technology and used in the VCOs. The VCOs oscillate in the K-band with PN of −111 and −110.4 dBc/Hz@1MHz offset at 21.3 and 23.1 GHz, for the single and double-ring resonators. The VCOs consume 2.2mW resulting in a Figure-of-Merit (FoM) of −193.9, −194.3, and −195dBc/Hz in the case of CSSR, DR, and Compacted DR resonators; respectively. The achieved FoM is 7 dB better than the obtained one using a conventional resonator (without SRR). The VCOs have good harmonic suppression of better than 26 dB between the fundamental and the second harmonic with an output power of −5.9dBm. Finally, the CSSRR and Compacted DRR VCOs have a core area of 0.031 mm2 and 0.021 mm2, respectively.

Low-Voltage Dual-Band CMOS Voltage-Controlled Oscillator for Ka-Band and V-Band Applications

A low-voltage dual-band CMOS voltage-controlled oscillator (VCO) is fabricated in a 90-nm CMOS process. The performance of the proposed VCO is improved by winding a multifunction inductor with transformer feedback and parasitic capacitance-splitting techniques. The proposed VCO adopts a push–push node to obtain a second-harmonic signal strengthened by using the injection amplifier and the bandpass filter. The measured tuning ranges of the fundamental signal and second-harmonic signal are from 27.5 to 30.04 and 55 to 60.08 GHz, respectively. The measured phase noise of the fundamental signal of 28.26 GHz is −95.62 and −111.5 dBc/Hz at 1- and 10-MHz offsets, respectively. The measured phase noise of the second-harmonic signal of 56.52 GHz is −87.83 and −107.9 dBc/Hz at 1- and 10-MHz offsets, respectively. The core power dissipation is 7.08 mW from a 0.6-V supply. The figure-of-merits (FOMs) and FOMs with tuning range (FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> s) at 1- and 10-MHz offsets are −176.1, −172, −175, and −170.9 dBc/Hz, respectively, from the fundamental signal of 28.26 GHz. The FOMs and FOM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> s at 1- and 10-MHz offsets are −174.3, −174.4, −173.2, and −173.3 dBc/Hz, respectively, from the second-harmonic signal of 56.52 GHz.

A 2.3–5-GHz LC-VCO With Source Damping Resistors to Suppress 1/f Noise Up-Conversion

Two RF CMOS voltage-controlled oscillators (VCOs) with source damping resistors to suppress 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise up-conversion are presented in this letter. Two important parameters: the phase deviation from the first harmonic term of the ideal impulse sensitivity function (ISF), and the initial phase of the first harmonic term of channel current, dominate the 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise up-conversion. Based on the outcome, the effects of the source damping resistors on the two phases are analyzed and two VCO prototypes are designed. Implemented in Taiwan Semiconductor Manufacturing Company 180 nm RF CMOS process, the VCOs achieve 64.7% and 50% frequency tuning range at 2.3–4.5 and 3–5 GHz, respectively, and perform phase noise (PN) of −131.03, −129.28, and −124.98 dBc/Hz at 1 MHz offset from output frequencies of 2.33, 3.057, and 4.57 GHz separately.

Single event transient mitigation techniques for a cross‐coupled LC oscillator, including a single‐event transient hardened CMOS LC‐VCO circuit

Single-event transients (SETs) due to heavy-ion (HI) strikes adversely affect the electronic circuits in the sub-100 nm regime in the radiation environment. This study proposes techniques to mitigate SETs in CMOS voltage-controlled oscillators (VCOs) without affecting the circuit specifications. A circuit asymmetry technique is used for faster recovery of the oscillator in the event of a single event transient (SET) caused by an ion hit. Also, a new SET tolerant inductor capacitor-voltage controlled oscillator (LC-VCO) topology is proposed for a radiation environment that shows reduced phase displacement, amplitude displacement, and recovery time. A comparison has been made with various LC-VCOs that have an inherent rad-hard capability which proves a significant improvement in SET sensitivity.

Design of power-efficient CMOS based oscillator circuit with varactor tuning control

This paper presents a low-power, wide tuning range CMOS voltage-controlled oscillator with MCML (MOS current mode logic) differential delay cell. Voltage controlled oscillator (VCO) circuit is designed in TSMC 0.25 μm CMOS process. To achieve the broad frequency range concept of variable capacitance is employed in the proposed VCO circuit. Source/drain tuning voltage (Vtune) and body bias voltage (Vb) of I-MOS varactor are used to achieve variable capacitance at different I-MOS varactor widths (W). The dual control voltage of I-MOS varactor results in a tuning range from 0.528 GHz to 2.014 GHz. VCO's figure of merit (FoM) is 152.13 dBc/Hz with phase noise of −93.77 dBc/Hz at 1 MHz offset from the oscillation frequency. The proposed VCO dissipates maximum power of 3.127 mW.

Design of optimal high-frequency CMOS VCOs for automotive application

In this paper, a design methodology of Voltage-Controlled Oscillator (VCO) for long-range automotive RAdio Detection And Ranging (RADAR) is proposed and simulation analysis is carried out over Virtuoso SpectreRF software on Cadence tool. The frequency ranges of the mm-wave CMOS current-starved ring and LC VCOs for 45-nm CMOS technology are 24 and 76 GHz, respectively. The ring VCO at 25 GHz oscillation frequency demonstrates 2.06% tuning range, phase noise −71.61 dBc/Hz at 1-MHz offset, 3.43 mW power dissipation and layout area of $$20\times 20 \,\upmu {\mathrm{m}}^2$$ whereas cross-coupled LC VCO achieves an oscillation frequency of 76.25 GHz for frequency tuning range of 0.65%, a phase noise of −92.44 dBc/Hz at 1-MHz offset, 8.59 mW power dissipation and $$320\times 320 \,\upmu {\mathrm{m}}^2$$ layout area. The proposed design of efficient VCOs shows an excellent performance for long-range automotive RADAR.

A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects

Class-C operation is leveraged to implement a $K$ -band CMOS voltage-controlled oscillator (VCO) where the upconversion of $1/f$ current noise from the cross-coupled transistors in the oscillator core is robustly contained at a very low level. Implemented in a bulk 28-nm CMOS technology, the 12%-tuning-range VCO shows a phase noise as low as −112 dBc/Hz at 1-MHz offset (−86 dBc/Hz at 100 kHz offset) from a 19.5 GHz carrier while consuming 20.7 mW, achieving a figure of merit (FoM) of −185 dBc/Hz. The design is complemented by a theoretical investigation of $1/f$ noise upconversion caused by short-channel effects in the cross-coupled transistors, obtaining the first instance of a closed-form phase noise expression in the $1/f^{3}$ region.

Radio frequency reliability studies of CMOS RF integrated circuits for ultra‐thin flexible packages

This Letter presents for the first time radio frequency (RF) reliability studies of fully integrated CMOS RF integrated circuits (RFICs) for next generation wireless communication applications involving conformal bodies where wireless communication RFICs will be embedded on ultra-thin flexible packages. As a test case, RF characteristics of a CMOS voltage-controlled oscillator (VCO) chip with multiple diesubstrate thicknesses were measured and results are analysed. The CMOS VCO chip under study was designed and fabricated using 180 nm RF-CMOS process. Reliability of performances of the VCO chips are characterised and results are compared before and after die thinning from 250 to 50, 35, and 25 μm, respectively. Critical RF performance parameters such as frequency of oscillation, output power, and phase noise are considered for analysis, respectively. All the dies are placed face-up for probing on the top of a metal chuck with ground connection inside the micro-chamber of a probe station. While the deviations of frequency and output power are within ±1% and ±1 dB, respectively, due to the die thinning affect, the phase noise deteriorations are observed significant. It confirms the wellknown fact of phase noise sensitiveness to the substrate thickness due to the leakage and SOI CMOS is discussed widely to minimise these parasitic effects. (Less)

Low-power low-phase noise VCO for 24 ​GHz applications

In this paper, CMOS voltage controlled-oscillator (VCO) with a frequency range of 22.7 ​GHz–27.9 ​GHz is presented. The scheme is modified current-reuse configuration, applicable to 5G applications. In the proposed configuration, the transistors are biased in subthreshold vicinity (VGS ​< ​VTH) to reduce power consumption. The usage of the capacitive feedback technique helps the output voltage to swing over the positive supply voltage and beneath the potential ground. The inclusion of the cross-coupled NMOS transistors with the inductive source degeneration enhance the transconductance and phase noise performance of VCO. The VCO has been implemented using 65 ​nm CMOS technology. The proposed VCO baised with 0.9 ​V and it showed the lowest power consumption of 1.35 ​mW and the lowest phase noise of −117 ​dBc/Hz at the 1 ​MHz offset frequency as compared to conventional results. This circuit also showed wide tuning range of 26.4%, low FOMT of −194.3 ​dBc/Hz, and small area in core die of 0.35 ​mm ​× ​0.35 ​mm. In addition, we have analyzed the mesaured output power spectrum of the proposed VCO using spectrum analyser (Anritsu, MS2760A) whereas the measured output power of the designed VCO is −7.9 dBm at the frequency of 24.5 ​GHz.

28-GHz CMOS VCO With Capacitive Splitting and Transformer Feedback Techniques for 5G Communication

This paper presents a 28-GHz low phase noise voltage-controlled oscillator (VCO) in a 65-nm CMOS process for 5G communication applications. With the capacitive splitting and transformer feedback techniques, theoretical analysis and simulations are undertaken for the proposed oscillator, proving that its negative G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> can be enhanced over the interested frequency range and reduced at the harmonic frequencies. Moreover, the proposed oscillator startup performance is analyzed, and its tank quality factor, transient and phase noise performance are simulated. With 4-bit switch capacitors and varactors, the proposed VCO achieves a tuning range from 25.7 to 29.7 GHz, consuming 10.8 mW from a 0.9-V supply voltage. With a wideband common-source buffer, the output signal power is around 1 dBm. At 26.5 GHz, the proposed VCO achieves low phase noise of -105.8 dBc/Hz at 1-MHz offset and -130 dBc/Hz at the 10-MHz offset, respectively.

Injection Pulling Mitigation in CMOS Voltage-Controlled Oscillator Using A Novel Honeycomb-Shaped Planar Inductor

This brief presents the injection pulling mitigation of a voltage-controlled oscillator (VCO) using a novel honeycomb-shaped planar inductor. Due to the twisted routes of the sub-coils in the proposed inductor, the interference caused by a nearby electromagnetic noise source can be compensated and reduced. By using a 0.18- ${\mu }\text{m}$ standard CMOS process, the proposed inductor and a conventional single-turn spiral inductor in a similar size are integrated into two respective VCO testchips. The injection pulling behaviors of these two oscillators are studied and compared. The experimental results show that the VCO integrated with the proposed honeycomb-shaped planar inductor can significantly mitigate the injection pulling phenomenon as compared with the VCO integrated with a conventional single-turn inductor in a similar size. In this brief, the enhancement of mitigation over 15 dB can be achieved.

Modelling and mitigation of single-event upset in CMOS voltage-controlled oscillator

Single-event effects (SEEs) have been the primary concern in study of radiation effects since late 1970s with the discovery of soft errors in terrestrial and space environments. The interaction of a single ionized particle with electronic devices leads to SEEs. In this paper, single-event upset (SEU) on CMOS devices in designing of a voltage-controlled oscillator (VCO) is analysed. Further, mitigation approaches of SEU are also discussed. To observe the impact of radiation, a VCO was designed in Cadence Virtuoso, and GDSII file of one ring oscillator stage was extracted to incorporate the same design in Silvaco MaskViews. With the help of layer map information file, masks were identified and used to design the CMOS inverter structure file for simulation of SEU condition. The input parameters for SEU simulation were evaluated from linear energy transfer (LET) graph of heavy ion under space conditions. The current profile of CMOS inverter was extracted under influence of a high-energy particle with the help of LET graph of that particle. This current profile was applied to different nodes of VCO and upset conditions were identified. Further, the impact of upset conditions on lock stage of phase-locked loop (PLL) is discussed. Results show that the SEU has significant impact on the logic state of inverters used in ring oscillator stage compared with current starving/biasing stage. The current profile of CMOS device has strong dependence on the energy of ion, its track, angle of incidence and the material. When angle of incidence is very less (\(7^{\circ }-14^{\circ }\)) the channel will be occupied by a funnel of charge and it leads to the maximum degradation of device. This work shows that a device operating at high frequency is more susceptible to SEU. Triple modular redundancy (TMR) and Radiation Hardened By Design (RHBD) can be used to mitigate SEU. TMR consumes more power and is less accurate compared with the RHBD approach.

A V-Band CMOS VCO With Digitally-Controlled Inductor for Frequency Tuning

This brief presents a digitally-controlled inductor (DCI) technique to tune the frequency of millimeter-wave (MMW) voltage controlled oscillators (VCOs). The design guideline, which is to structure a larger coupled inductor when obtaining a required inductance, is derived to optimize the quality factor. To extend the tuning range and minimize the ${Q}$ degradation, a DCI composed of a primary coil and two switched secondary coils is designed and proposed. Switching the two secondary coils on and off, individually, effective inductance seen from the primary coil for LC oscillation is varied. Implemented in a 65 nm CMOS process, the MMW VCO prototype employing the DCI measures a 14% frequency tuning range from 49.2 to 56.6 GHz, phase noise from −87 to −93 dBc/Hz at 1-MHz offset, and the state-of-the-art FOM $_{A}$ of −196.3 dBc/Hz, while consuming dc power of 7.2 mW and occupying small core area of only 0.02 mm2.

A 2.4 GHz Low Power Low Phase-Noise Enhanced FOM VCO for RF Applications Using 180 nm CMOS Technology

The Voltage Controlled Oscillator (VCO) is an important component of the transceiver which consumes significant energy as compared to the other transceiver components. Since RF application systems such as WiFi, Bluetooth or Zigbee uses battery energy, it is necessary to reduce the power consumption while maintaining reasonable system performance. In this work, the performance of standard VCOs is studied and a new design method of CMOS VCO is proposed. The architecture of the proposed VCO is based on the negative resistance based LC tank circuit using MOSFET. The performance of the proposed VCO is compared in terms of phase noise, figure-of-merit (FOM) and power consumption. The phase noise and FOM of the proposed design is ýý124 and ýý187.25 dBc/Hz respectively at 1 MHz offset frequency with power consumption of 2.86 mW. It has been observed that the proposed VCO can be a suitable candidate for low power RF circuit applications while maintaining reasonable performance metrics.