CMOS Transmission Line Research Articles

Parametric Analysis and Design Guidelines for mm-Wave Transmission Lines in nm CMOS

This paper focuses on nm CMOS transmission line design as distributed passive elements and their application in mm-wave integrated circuits. A variety of transmission lines such as coplanar waveguides (CPWs), shielded coplanar waveguides (SCPWs), and CPW with ground are analyzed in terms of their geometry and electrical properties. The parametric analysis of the various line types is based on a combination of experimental and simulated data. The slow wave effect of the SCPW is proved to result in better performance, size reduction, and reduced costs compared to the regular CPW. From parametric analysis, a simple set of tests is derived that can easily indicate the capabilities of a certain process design kit in terms of a transmission line design. Finally, in an effort to further reduce silicon area and respective cost, a design technique is proposed with a semilumped CPW transmission line using metal–oxide–metal capacitors as loading elements. This semilumped CPW design achieves nearly double-phase constant per length over the regular CPW and is highly attractive for mm-wave CMOS design.

A Technique to Reduce On-Wafer Measurement Uncertainty for CMOS Transmission Line Characterization

An improvement to the L-L method for Si monolithic Transmission Line (TL) parameter extraction is presented. The propagation constant $\gamma$ and characteristic impedance ${\rm Z}_{0}$ are obtained from cascaded ABCD matrices using on-wafer measurements up to 40 GHz. It is shown that the L-L method matrices processing is strongly dependent on the access variations as different pairs of measurements lead to different extracted TL parameters. Associating three different TLs lengths test structures measurements matrices, which theoretically point to an identity matrix, a technique is proposed to obtain the best set of three measurements with the most similar accesses. The deviation from the ideal identity matrix indicates the access variations. The suggested technique was implemented with TL structures fabricated on a 130 nm CMOS process. When using the best set of three different TL length measurements, the extracted $\gamma$ and ${\rm Z}_{0}$ parameters are almost independent on the TL pair used.

A spatial sampling based 13.3 Gs/s sample-and-hold circuit.

This paper presents a high-speed sample-and-hold circuit (SHC) for very fast signal analysis. Spatial sampling techniques are exploited with CMOS transmission lines in a 0.13 μm standard CMOS process. The SHC includes on chip coplanar waveguides for signal and clock pulse transmission, a clock pulse generator, and three elementary samplers periodically (L = 7.2 mm) placed along the signal propagation line. The SHC samples at 13.3 Gs/s. The circuit occupies an area of 1660 μm × 820 μm and consumes ~6 mW at a supply voltage of 1.2 V. The obtained input bandwidth is ~11.5 GHz.

Modeling of Short-Millimeter-Wave CMOS Transmission Line with Lossy Dielectrics with Specific Absorption Spectrum

On-chip transmission lines are widely used in ultrahigh-frequency integrated circuits. One of the issues in modeling such transmission lines is that no reference impedance can be established on a chip. Conventionally, the parallel admittance Yp has been adopted as a reference parameter for on-chip transmission lines instead of a reference characteristic impedance of 50Ω. In the case of CMOS processes, however, Yp can have complicated characteristics in the short-millimeter-wave band owing to the frequency characteristics of the electric permittivity of low-k materials, which cannot be expressed using a simple circuit. To solve this problem, we propose the use of the series impedance Zs as a reference parameter for transmission-line modeling since it basically can be determined from the geometrical dimensions and the frequency-stable permeability and resistivity. The parameters of transmission lines obtained by the proposed method were compared with those obtained by conventional methods using a 40nm CMOS process. By using the equivalent circuit model of Yp along with RLC resonators, it is shown that the peaks of the frequency characteristics of Yp can be used to explain the absorption spectrum of the dielectric. This suggests that the proposed method is suitable for CMOS short-millimeter-wave transmission lines.

A high-speed sample-and-hold circuit based on CMOS transmission lines

We introduce the design of a high-speed sample-and-hold circuit (SHC) based on spatial sampling with CMOS transmission lines (TLs). Signal propagation analysis shows that periodically loaded CMOS T...

Millimeter‐wave low‐loss transmission lines and resonators in standard 0.18‐μm CMOS technology

AbstractDesign methodologies of CMOS transmission lines (T‐lines) and resonators at millimeter‐wave frequencies are presented. Three different T‐lines including thin film microstrip line, coplanar waveguide, coplanar waveguide with ground, are designed and fabricated in standard 0.18‐μm CMOS technology. After on‐wafer testing to 40 GHz and SLOT de‐embedding calibration, their S‐parameters are extracted and analyzed. To achieve a small size, meandering quarter‐wavelength line resonator and stepped impedance resonator resonating near 30 GHz are designed, with their Q‐factor of 12 and 10.5, respectively. A good agreement between the predicted and measured results has been observed up to 40 GHz. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1579–1582, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23424